Patents by Inventor Gerald Ofner

Gerald Ofner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160358848
    Abstract: A microelectronic package including a passive microelectronic device disposed within a package body, wherein the package body is the portion of the microelectronic package which provides support and/or rigidity to the microelectronic package. In a flip-chip type microelectronic package, the package body may comprise a microelectronic substrate to which an active microelectronic device is electrically attached. In an embedded device type microelectronic package, the package body may comprise the material in which the active microelectronic device is embedded.
    Type: Application
    Filed: March 12, 2014
    Publication date: December 8, 2016
    Applicant: INTEL CORPORATION
    Inventors: Thorsten Meyer, Gerald Ofner, Andreas Wolter, Georg Seidemann, Sven Albers, Christian Geissler
  • Patent number: 9472515
    Abstract: Embodiments of the present disclosure are directed towards a method of assembling an integrated circuit package. In embodiments the method may include providing a wafer having an unpatterned passivation layer to prevent corrosion of metal conductors embedded in the wafer. The method may further include laminating a dielectric material on the passivation layer to form a dielectric layer and selectively removing dielectric material to form voids in the dielectric layer. These voids may reveal portions of the passivation layer disposed over the metal conductors. The method may then involve removing the portions of the passivation layer to reveal the metal conductors. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: March 11, 2014
    Date of Patent: October 18, 2016
    Assignee: INTEL CORPORATION
    Inventors: Thorsten Meyer, Gerald Ofner, Teodora Ossiander, Frank Zudock, Christian Geissler
  • Publication number: 20160260689
    Abstract: A package-on-package stacked microelectronic structure comprising a pair of microelectronic packages attached to one another in a flipped configuration. In one embodiment, the package-on-package stacked microelectronic structure may comprise a first and a second microelectronic package, each comprising a substrate having at least one package connection bond pad formed on a first surface of each microelectronic package substrate, and each having at least one microelectronic device electrically connected to the each microelectronic package substrate first surface, wherein the first and the second microelectronic package are connected to one another with at least one package-to-package interconnection structure extending between the first microelectronic package connection bond pad and the second microelectronic package connection bond pad.
    Type: Application
    Filed: July 7, 2014
    Publication date: September 8, 2016
    Applicant: INTEL IP CORPORATION
    Inventors: Thorsten Meyer, Gerald Ofner
  • Publication number: 20160200566
    Abstract: In embodiments, a package assembly may include an application-specific integrated circuit (ASIC) and a microelectromechanical system (MEMS) having an active side and an inactive side. In embodiments, the MEMS may be coupled directly to the ASIC by way of one or more interconnects. The MEMS, ASIC, and one or more interconnects may define or form a cavity such that the active portion of the MEMS is within the cavity. In some embodiments, the package assembly may include a plurality of MEMS coupled directly to the ASIC by way of a plurality of one or more interconnects. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: June 28, 2013
    Publication date: July 14, 2016
    Applicant: Intel IP Corporation
    Inventors: Gerald Ofner, Thorsten Meyer, Reinhard Mahnkopf, Christian Geissler, Andreas Augustin
  • Patent number: 9385105
    Abstract: A semiconductor device includes: a chip having at least one electrically conductive contact at a first side of the chip; an extension layer extending laterally from one or more sides of the chip; a redistribution layer on a surface of the extension layer and the first side, and coupled to the contact; an interposer having at least one electrically conductive contact at a first surface of the interposer and coupled to the redistribution layer, and at least one electrically conductive contact at a second surface of the interposer opposite to the first surface; a molding material at least partially enclosing the chip and the redistribution layer, and in contact with the interposer. Another semiconductor device includes: an interposer; a redistribution layer over the interposer; a circuit having first and second circuit portions, wherein the redistribution layer includes the first circuit portion, and the interposer includes the second circuit portion.
    Type: Grant
    Filed: January 10, 2013
    Date of Patent: July 5, 2016
    Assignee: Intel Deutschland GmbH
    Inventors: Thorsten Meyer, Gerald Ofner, Bernd Waidhas, Hans-Joachim Barth, Sven Albers, Reinhard Golly, Philipp Riess, Bernd Ebersberger
  • Patent number: 9263376
    Abstract: A chip interposer may include: a first interconnect level including a first pad; and a second interconnect level including a second pad, wherein the second pad may face in the same direction as the first pad.
    Type: Grant
    Filed: April 15, 2013
    Date of Patent: February 16, 2016
    Assignee: INTEL DEUTSCHLAND GMBH
    Inventors: Thorsten Meyer, Gerald Ofner
  • Publication number: 20150282308
    Abstract: Passive electrical devices are described with a polymer carrier. In one example, a conductive layer is formed over a polymer substrate in a pattern to form a passive electrical device and at least two terminals of the device. A plurality of external connection pads are connected to the terminals of the device.
    Type: Application
    Filed: March 28, 2014
    Publication date: October 1, 2015
    Inventors: Thorsten Meyer, Gerald Ofner, Sven Albers, Reinhard Mahnkopf
  • Publication number: 20150266728
    Abstract: Stress buffer layers for integrated microelectromechanical systems (MEMS) are described. For example, a semiconductor package includes a substrate having first and second surfaces, the second surface having an array of external conductive contacts. A microelectromechanical system (MEMS) component is disposed above the first surface of the substrate. A buffer layer is disposed above the MEMS component, the buffer layer having a first Young's modulus. A mold compound is disposed above the buffer layer, the mold compound having a second Young's modulus higher than the first Young's modulus.
    Type: Application
    Filed: June 4, 2015
    Publication date: September 24, 2015
    Inventors: Christian Geissler, Thorsten Meyer, Gerald Ofner, Reinhard Mahnkopf, Andreas Augustin, Christian Mueller
  • Publication number: 20150262866
    Abstract: Embodiments of the present disclosure are directed towards a method of assembling an integrated circuit package. In embodiments the method may include providing a wafer having an unpatterned passivation layer to prevent corrosion of metal conductors embedded in the wafer. The method may further include laminating a dielectric material on the passivation layer to form a dielectric layer and selectively removing dielectric material to form voids in the dielectric layer. These voids may reveal portions of the passivation layer disposed over the metal conductors. The method may then involve removing the portions of the passivation layer to reveal the metal conductors. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: March 11, 2014
    Publication date: September 17, 2015
    Inventors: Thorsten Meyer, Gerald Ofner, Teodora Ossiander, Frank Zudock, Christian Geissler
  • Patent number: 9059304
    Abstract: According to various embodiments, a flip chip package structure is provided in which a redistribution layer (RDL) is disposed on a surface of both a semiconductor chip and one or more lateral extensions of the semiconductor chip surface. The lateral extensions may be made using, e.g., a reconstituted wafer to implement a fanout region lateral to one or more sides of the semiconductor chip. One or more electrical connectors such as solder bumps or copper cylinders may be applied to the RDL, and an interposer such as a PCB interposer may be connected to the electrical connectors. In this way, a relatively tight semiconductor pad pitch may be accommodated and translated to an appropriate circuit board pitch without necessarily requiring a silicon or glass interposer.
    Type: Grant
    Filed: January 27, 2014
    Date of Patent: June 16, 2015
    Assignee: INTEL MOBILE COMMUNICATIONS GMBH
    Inventors: Thorsten Meyer, Gerald Ofner, Bernd Waidhas
  • Patent number: 9056763
    Abstract: Stress buffer layers for integrated microelectromechanical systems (MEMS) are described. For example, a semiconductor package includes a substrate having first and second surfaces, the second surface having an array of external conductive contacts. A microelectromechanical system (MEMS) component is disposed above the first surface of the substrate. A buffer layer is disposed above the MEMS component, the buffer layer having a first Young's modulus. A mold compound is disposed above the buffer layer, the mold compound having a second Young's modulus higher than the first Young's modulus.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: June 16, 2015
    Assignee: Intel Corporation
    Inventors: Christian Geissler, Thorsten Meyer, Gerald Ofner, Reinhard Mahnkopf, Andreas Augustin, Christian Mueller
  • Publication number: 20150091167
    Abstract: Stress buffer layers for integrated microelectromechanical systems (MEMS) are described. For example, a semiconductor package includes a substrate having first and second surfaces, the second surface having an array of external conductive contacts. A microelectromechanical system (MEMS) component is disposed above the first surface of the substrate. A buffer layer is disposed above the MEMS component, the buffer layer having a first Young's modulus. A mold compound is disposed above the buffer layer, the mold compound having a second Young's modulus higher than the first Young's modulus.
    Type: Application
    Filed: September 27, 2013
    Publication date: April 2, 2015
    Inventors: Christian Geissler, Thorsten Meyer, Gerald Ofner, Reinhard Mahnkopf, Andreas Augustin, Christian Mueller
  • Publication number: 20150028478
    Abstract: A semiconductor device includes: a chip having at least one electrically conductive contact at a first side of the chip; an extension layer extending laterally from one or more sides of the chip; a redistribution layer on a surface of the extension layer and the first side, and coupled to the contact; an interposer having at least one electrically conductive contact at a first surface of the interposer and coupled to the redistribution layer, and at least one electrically conductive contact at a second surface of the interposer opposite to the first surface; a molding material at least partially enclosing the chip and the redistribution layer, and in contact with the interposer. Another semiconductor device includes: an interposer; a redistribution layer over the interposer; a circuit having first and second circuit portions, wherein the redistribution layer includes the first circuit portion, and the interposer includes the second circuit portion.
    Type: Application
    Filed: January 10, 2013
    Publication date: January 29, 2015
    Inventors: Thorsten Meyer, Gerald Ofner, Bernd Waidhas, Hans-Joachim Barth, Sven Albers, Reinhard Golly, Philipp Riess, Bernd Ebersberger
  • Publication number: 20140361387
    Abstract: A chip arrangement may include: a mold compound; and a microelectromechanical systems device at least partially embedded in the mold compound.
    Type: Application
    Filed: June 5, 2013
    Publication date: December 11, 2014
    Inventors: Thorsten Meyer, Gerald Ofner, Christian Mueller, Reinhard Mahnkopf, Christian Geissler, Andreas Augustin
  • Patent number: 8878360
    Abstract: A stacked semiconductor device and method of manufacturing a stacked semiconductor device are described. The semiconductor device may include a reconstituted base layer having a plurality of embedded semiconductor chips. A first redistribution layer may contact the electrically conductive contacts of the embedded chips and extend beyond the boundary of one or more of the embedded chips, forming a fan-out area. Another chip may be stacked above the chips embedded in the base layer and be electrically connected to the embedded chips by a second redistribution layer. Additional layers of chips may be included in the semiconductor device.
    Type: Grant
    Filed: July 13, 2012
    Date of Patent: November 4, 2014
    Assignee: Intel Mobile Communications GmbH
    Inventors: Thorsten Meyer, Gerald Ofner, Sven Albers
  • Publication number: 20140306355
    Abstract: A chip interposer may include: a first interconnect level including a first pad; and a second interconnect level including a second pad, wherein the second pad may face in the same direction as the first pad.
    Type: Application
    Filed: April 15, 2013
    Publication date: October 16, 2014
    Inventors: Thorsten Meyer, Gerald Ofner
  • Patent number: 8754522
    Abstract: Repairable semiconductor device and method. In one embodiment a method, provides a first body having a first semiconductor chip and a first metal layer. A second body includes a second semiconductor chip and a second metal layer. Metal of the first metal layer is removed. The first semiconductor chip is removed from the first body. The second body is attached to the first body. The first metal layer is electrically coupled to the second metal layer.
    Type: Grant
    Filed: October 26, 2011
    Date of Patent: June 17, 2014
    Assignee: Infineon Technologies AG
    Inventors: Thorsten Meyer, Gerald Ofner
  • Patent number: 8741690
    Abstract: A method of manufacturing a semiconductor package includes embedding a semiconductor chip in an encapsulant. First contact pads are formed on a first main face of the semiconductor package and second contact pads are formed on a second main face of the semiconductor package opposite the first main face. A diameter d in micrometers of an exposed contact pad area of the second contact pads satisfies d?(8/25)x+142 ?m, where x is a pitch of the second contact pads in micrometers.
    Type: Grant
    Filed: April 23, 2012
    Date of Patent: June 3, 2014
    Assignee: Infineon Technologies AG
    Inventors: Thorsten Meyer, Rainer Leuschner, Gerald Ofner, Reinhard Hess, Recai Sezi
  • Publication number: 20140138827
    Abstract: According to various embodiments, a flip chip package structure is provided in which a redistribution layer (RDL) is disposed on a surface of both a semiconductor chip and one or more lateral extensions of the semiconductor chip surface. The lateral extensions may be made using, e.g., a reconstituted wafer to implement a fanout region lateral to one or more sides of the semiconductor chip. One or more electrical connectors such as solder bumps or copper cylinders may be applied to the RDL, and an interposer such as a PCB interposer may be connected to the electrical connectors. In this way, a relatively tight semiconductor pad pitch may be accommodated and translated to an appropriate circuit board pitch without necessarily requiring a silicon or glass interposer.
    Type: Application
    Filed: January 27, 2014
    Publication date: May 22, 2014
    Inventors: Thorsten Meyer, Gerald Ofner, Bernd Waidhas
  • Patent number: 8716859
    Abstract: A flip chip package structure is proposed in which a redistribution layer (RDL) is disposed on a surface of both a semiconductor chip and one or more lateral extensions of the semiconductor chip surface. The lateral extensions may be made using, e.g., a reconstituted wafer to implement a fanout region lateral to one or more sides of the semiconductor chip. One or more electrical connectors such as solder bumps or copper cylinders may be applied to the RDL, and an interposer such as a PCB interposer may be connected to the electrical connectors. In this way, a relatively tight semiconductor pad pitch may be accommodated and translated to an appropriate circuit board pitch without necessarily requiring a silicon or glass interposer.
    Type: Grant
    Filed: January 10, 2012
    Date of Patent: May 6, 2014
    Assignee: Intel Mobile Communications GmbH
    Inventors: Thorsten Meyer, Gerald Ofner, Bernd Waidhas