Abstract: A test apparatus for semiconductor modules. One embodiment provides a test system. The test system includes a handler configured to receive at least one semiconductor module. The test system is equipped with a plurality of different pin cards. The handler has at least two independent groups of test receptacles.

Abstract: The present invention provides an apparatus for monitoring a state, in particular of a fuse (4), having: a first state storage device (11) for storing a state, in particular of a fuse (4); a second state storage device (12) for storing the state of the first state storage device (11); and a logic device (9) for comparing the states of the two state stores (11, 12); the first state store (11) being able to be driven for renewed reading in of the state, in particular of the fuse (4), in the event of a noncorrespondence of the states in the two stores (11, 12). The present invention likewise provides a method for monitoring a state, in particular of a fuse.

Abstract: Method for determining a repair solution for a memory module in a test system, memory areas of the memory module being successively tested in order to obtain, for each memory area, a defect datum which specifies whether the respective memory area is defective, wherein defect addresses, the address values of which specify the defective memory areas of the memory module, are generated from addresses of the memory areas and the associated defect data, the defect addresses being stored in the test system, the repair solution being determined from the stored defect addresses.

Abstract: An integrated circuit is provided, the integrated circuit having a test circuit for reading out an error datum from the integrated circuit in accordance with a test mode, wherein the error datum is output via a first and a second data output, and wherein an address and a read command are applied to the integrated circuit to read out the error datum associated with the address via one of the data outputs. The test circuit is configured in such a manner that, when a first read command is applied, the test circuit outputs the error datum at the first data output and switches the second data output to high impedance and, when a second read command is applied, the test circuit outputs the error datum at the second data output and switches the first data output to high impedance.

Abstract: The invention relates to a test system for testing connectable integrated circuits. A particular test system may have switching devices via which a respective assigned one of the integrated circuits can be connected to the supply unit, a control unit for controlling the switching devices, and a determination unit in order to determine an item of information about a power consumption of an integrated circuit to be measured. The control unit, depending on the information, may switch the switching device in order to connect the integrated circuit to be measured to the supply unit or to isolate it from the supply unit.

Abstract: A system and method for testing an integrated circuit is provided. In one embodiment, a method includes comparing the signal level of the output signal of the integrated circuit to the signal level of a reference signal, wherein a comparison signal is output, which has a first or a second value depending on whether the actual signal level of the output signal is above or below the actual signal level of the reference signal; determining the value of the comparison signal at a certain time; evaluating the value of the comparison signal determined at the time by way of a default; and outputting an error signal if the determined value of the comparison signal does not correspond to the default.

Abstract: A system and method for testing an integrated circuit is provided. In one embodiment, a method includes comparing the signal level of the output signal of the integrated circuit to the signal level of a reference signal, wherein a comparison signal is output, which has a first or a second value depending on whether the actual signal level of the output signal is above or below the actual signal level of the reference signal; determining the value of the comparison signal at a certain time; evaluating the value of the comparison signal determined at the time by way of a default; and outputting an error signal if the determined value of the comparison signal does not correspond to the default.

Abstract: Methods and apparatus for testing a semiconductor device. A testing interface is configured to interface with an external test apparatus and a device under test (DUT). In one embodiment, the testing interface receives test data and a test clock signal from the external test apparatus. The test data is clocked out of the testing interface and to the DUT according to the test clock signal. Further, the test clock signal is delayed by a period of time and then a delayed clock signal is issued to the device. The data previously written to the DUT is read out of the DUT and compared with the test data received from the external test apparatus. The period of time by which the test clock signal is delayed can be varied to achieve a desired timing.

Abstract: The invention relates to a module having a first integrated circuit and a second integrated circuit which are arranged on separate substrates, having a first output terminal and a second output terminal to which the first and second integrated circuits are respectfully connected in a parallel manner, and having a first selection terminal and a second selection terminal which are mutually separate and are connected to the first and second integrated circuits, respectively. A test circuit is provided in each of the integrated circuits to generate an error signal depending on whether an error occurred during a test operation, and an output circuit is provided in each of the integrated circuits to select the first output terminal or the second output terminal, depending on a selection signal that is applied to the respective selection terminal, for the purpose of outputting a state that indicates the error.

Abstract: A process for producing a component module comprising a module carrier and a plurality of components with which contact is made on the latter, comprising the following steps: arranging separated components on a surface-adhesive film at a predefined contact-specific spacing from one another, embedding the components in a flexible material in order to form a flexible holding frame which holds the components, pulling off the film, producing contact-making elements on the exposed side of the components, performing a functional test of the components and, if necessary, repair and/or replacement of components, and fixing and making contact with the components held in the holding frame on the module carrier.

Abstract: Test system for testing integrated chips and an adapter element for a test system.

Abstract: A level shifting circuit includes a level-shifting section responsive to an input logic signal, which varies between a first voltage level (e.g., ground) and a second voltage level (e.g., 2.1V). The level-shifting section provides an output logic signal at an output terminal. The output logic signal varies between the first voltage level and a third voltage level (e.g., 2.5V). The circuit also includes an enable/disable section with a first portion coupled between the level shifting section and a first reference voltage node (e.g., ground) and a second portion coupled between the level shifting section and the third reference voltage node. The enable/disable section causes the output terminal to be placed at a relatively high output impedance condition independent of the logic state of the input logic signal in response to a disable mode indication from an enable/disable signal.

Abstract: An integrated circuit is provided, the integrated circuit having a test circuit for reading out an error datum from the integrated circuit in accordance with a test mode, wherein the error datum is output via a first and a second data output, and wherein an address and a read command are applied to the integrated circuit to read out the error datum associated with the address via one of the data outputs. The test circuit is configured in such a manner that, when a first read command is applied, the test circuit outputs the error datum at the first data output and switches the second data output to high impedance and, when a second read command is applied, the test circuit outputs the error datum at the second data output and switches the first data output to high impedance.

Abstract: The invention relates to a test system for testing connectable integrated circuits. A particular test system may have switching devices via which a respective assigned one of the integrated circuits can be connected to the supply unit, a control unit for controlling the switching devices, and a determination unit in order to determine an item of information about a power consumption of an integrated circuit to be measured. The control unit, depending on the information, may switch the switching device in order to connect the integrated circuit to be measured to the supply unit or to isolate it from the supply unit.

Abstract: The present invention provides a method for fabricating semiconductor circuit modules having the following steps: application of a patterned connection layer to a transfer substrate, application of active circuit devices and/or passive circuit devices with contact areas pointing toward the patterned connection layer, connection of the circuit devices to one another by means of a filler at least between the circuit devices, removal of the transfer substrate, and application of electrical connection devices for selective contact connection of the contact area of the circuit devices to one another.

Abstract: A calibration device for the calibration of a tester channel of a tester device is provided. The calibration device includes a connecting device and a planar contact carrier with a first contact area and a second contact area insulated from the first contact area, the first contact area being generally surrounded by the second contact area, so that, when a needle card connected to the tester device is placed onto the contact carrier of the calibration device, one of the contact-connecting needles of the needle card which is connected to the tester channel to be calibrated is placed onto the first contact area and a plurality or all of the further contact-connecting needles of the needle card at tester channels that are not to be calibrated are placed onto the second contact area.

Abstract: A semiconductor packaging arrangement, or module, includes a printed circuit board having an electrical interconnect thereon and a semiconductor package mounted to the printed circuit board. The semiconductor package includes a fractional portion of a semiconductor wafer having a plurality of integrated circuit chips thereon, such chips being separated by regions in the fractional portion of the wafer. The fractional portion of the wafer has a plurality of electrical contacts electrically connected to the chips. The package also includes a dielectric member having an electrical conductor thereon. The electrical conductor are electrically connected to the plurality of electrical contacts of the plurality of chips to electrically interconnect such plurality of chips with portions of the electrical conductor spanning the regions in the fractional portion of the wafer.

Abstract: The invention relates to an integrated test circuit in an integrated circuit for testing a plurality of internal voltages. A switching device is provided to select one of the internal voltages in accordance with a selection signal for the purpose of testing, and a comparator device is provided in order to compare a measurement voltage, dependent on the selected internal voltage, with an externally provided reference voltage. An error signal is output as a result of the comparison.

Abstract: Methods and apparatus for testing a semiconductor device. A testing interface is configured to interface with an external test apparatus and a device under test (DUT). In one embodiment, the testing interface receives test data and a test clock signal from the external test apparatus. The test data is clocked out of the testing interface and to the DUT according to the test clock signal. Further, the test clock signal is delayed by a period of time and then a delayed clock signal is issued to the device. The data previously written to the DUT is read out of the DUT and compared with the test data received from the external test apparatus. The period of time by which the test clock signal is delayed can be varied to achieve a desired timing.

Abstract: A method of recording test information to identify a location of errors in Integrated Circuits (ICs) includes scanning a plurality of ICs with an input signal, each IC having a plurality of data locations and comparing an output response at each data location with an expected value for the data location. The method also includes storing an address in a buffer for each data location where the response at the data location does not equal the expected value corresponding to the data location.