Abstract: The invention provides a method for activating fuse units (101a-101n) in an electronic circuit device (100) in order to modify a circuit design for the electronic circuit device (100), where an electronic circuit device (100) in which fuse units (101a-101n) can be activated is selected, those fuse units (101a-101n) in the selected electronic circuit device (100) which can be activated in order to modify the circuit design for the electronic circuit device (100) are determined, the fuse units (101a-101n) which can be activated in order to mosdify the circuit design for the electronic circuit device (100) are addressed using fuse addressing units (102a-102n), and an activation state of the fuse units (101a-101n) which can be activated in order to modify the circuit design for the electronic circuit device (100) is stipulated, the fuse units (101a-101n) addressed using the fuse addressing units (102a-102n) being activated using fuse activation units (103a-103n) in line with the stipulated activation state.

Abstract: The invention relates to a module having a first integrated circuit and a second integrated circuit which are arranged on separate substrates, having a first output terminal and a second output terminal to which the first and second integrated circuits are respectfully connected in a parallel manner, and having a first selection terminal and a second selection terminal which are mutually separate and are connected to the first and second integrated circuits, respectively. A test circuit is provided in each of the integrated circuits to generate an error signal depending on whether an error occurred during a test operation, and an output circuit is provided in each of the integrated circuits to select the first output terminal or the second output terminal, depending on a selection signal that is applied to the respective selection terminal, for the purpose of outputting a state that indicates the error.

Abstract: The embodiments of the present invention are directed to a self-repair schema for memory chips, using a sortable fail-count/fail-address register. The embodiments of the present invention utilize the available redundancy efficiently by scanning the memory array to locate the n elements (WLs or CSLs) with the highest number of defects. A circuit preferably comprises one or more comparators to compare a fail count of an address in an input register with at least one fail count stored in the sortable fail-count/fail-address register. The embodiments of the present invention can be used for an on-chip redundancy calculation and can handle a two dimensional (i.e. row and column) redundancy.

Abstract: Described are integrated circuit chips that are capable of self-adjusting an internal voltage of the integrated circuit chip and methods for adjusting the internal voltage of an integrated circuit chip. The methods include comparing an internally generated voltage to an external target voltage.

Abstract: A multi-chip module having an integrated semiconductor mass memory and a logic chip is disclosed. In accordance with one aspect of the invention, the integrated logic chip includes electrically programmable links or other non-volatile memory for permanently storing memory cells of the memory chip identified as defective. In the event of accesses to the memory chip the address present is compared with the stored addresses of the defective cells by a comparator and, if appropriate, a changeover is made from the memory chip to a volatile memory provided for this purpose in the logic chip, in which redundant memory cells are formed. The result is a significantly increased yield and a reduced test complexity, particularly in mass production.

Abstract: One embodiment of the invention provides a calibration device for the calibration of a tester channel of a tester device to which integrated components on a substrate wafer can be contact-connected for testing with electrical signals.

Abstract: A level shifting circuit includes a level-shifting section responsive to an input logic signal, which varies between a first voltage level (e.g., ground) and a second voltage level (e.g., 2.1 V). The level-shifting section provides an output logic signal at an output terminal. The output logic signal varies between the first voltage level and a third voltage level (e.g., 2.5V). The circuit also includes an enable/disable section with a first portion coupled between the level shifting section and a first reference voltage node (e.g., ground) and a second portion coupled between the level shifting section and the third reference voltage node. The enable/disable section causes the output terminal to be placed at a relatively high output impedance condition independent of the logic state of the input logic signal in response to a disable mode indication from an enable/disable signal.

Abstract: A system and method is provided for controlling the impedance and current of an off chip driver circuit to match to load driven by the driver and for reducing noise and ringing in the off chip driver circuit. The driver comprises a pull up transistor for switching the output of the driver to a high-voltage, a pull down transistor for switching the output of the driver to a low voltage, a first current mirror transistor coupled to the pull up transistor for controlling the current transmitted to a load connected to the driver when the output of the driver is at the high-voltage, and a second current mirror transistor coupled to the pull down transistor for controlling the current transmitted to the load when the output of the driver is at the low voltage. In addition, the driver may include a first pre-driver providing a gate signal for the pull up transistor having a controlled slew rate and a second pre-driver providing a gate signal for the pull down transistor having a controlled slew rate.

Abstract: Test system for testing integrated chips and an adapter element for a test system.

Abstract: The embodiments of the present invention are directed to a self-repair schema for memory chips, using a sortable fail-count/fail-address register. The embodiments of the present invention utilize the available redundancy efficiently by scanning the memory array to locate the n elements (WLs or CSLs) with the highest number of defects. A circuit preferably comprises one or more comparators to compare a fail count of an address in an input register with at least one fail count stored in the sortable fail-count/fail-address register. The embodiments of the present invention can be used for an on-chip redundancy calculation and can handle a two dimensional (i.e. row and column) redundancy.

Abstract: The invention creates a method for connection of circuit units (101a-10n) which are arranged on a wafer (100), in which the wafer (100) is fitted to a first film (102a), the wafer (100) is sawn such that the circuit units (101a-101n) which are arranged on the wafer (100) are separated, the functional circuit units (101d) are picked up by means of a handling device (101) and are placed down on a second film (102b) by means of the handling device (103), so as to produce a separation distance which can be predetermined between connection contacts of the circuit units (101d).

Abstract: A semiconductor packaging arrangement, or module, includes a printed circuit board having an electrical interconnect thereon and a semiconductor package mounted to the printed circuit board. The semiconductor package includes a fractional portion of a semiconductor wafer having a plurality of integrated circuit chips thereon, such chips being separated by regions in the fractional portion of the wafer. The fractional portion of the wafer has a plurality of electrical contacts electrically connected to the chips. The package also includes a dielectric member having an electrical conductor thereon. The electrical conductor are electrically connected to the plurality of electrical contacts of the plurality of chips to electrically interconnect such plurality of chips with portions of the electrical conductor spanning the regions in the fractional portion of the wafer.

Abstract: The invention relates to an integrated circuit having a test circuit and a test terminal, it being possible for the test circuit to be activated by means of a test signal which can be applied to the test terminal in order to start a test function, a switching device being provided in order, after the activation of the test circuit, to connect the test terminal to an internal voltage line, in order to supply a current requirement needed on account of the test function that is performed.

Abstract: The invention relates to an integrated test circuit in an integrated circuit for testing a plurality of internal voltages. A switching device is provided to select one of the internal voltages in accordance with a selection signal for the purpose of testing, and a comparator device is provided in order to compare a measurement voltage, dependent on the selected internal voltage, with an externally provided reference voltage. An error signal is output as a result of the comparison.

Abstract: Method for determining a repair solution for a memory module in a test system, memory areas of the memory module being successively tested in order to obtain, for each memory area, a defect datum which specifies whether the respective memory area is defective, wherein defect addresses, the address values of which specify the defective memory areas of the memory module, are generated from addresses of the memory areas and the associated defect data, the defect addresses being stored in the test system, the repair solution being determined from the stored defect addresses.

Abstract: A semiconductor packaging arrangement, or module, includes a printed circuit board having an electrical interconnect thereon and a semiconductor package mounted to the printed circuit board. The semiconductor package includes a fractional portion of a semiconductor wafer having a plurality of integrated circuit chips thereon, such chips being separated by regions in the fractional portion of the wafer. The fractional portion of the wafer has a plurality of electrical contacts electrically connected to the chips. The package also includes a dielectric member having an electrical conductor thereon. The electrical conductor are electrically connected to the plurality of electrical contacts of the plurality of chips to electrically interconnect such plurality of chips with portions of the electrical conductor spanning the regions in the fractional portion of the wafer.

Abstract: Address information representing failed elements in an array portion of a device is delivered. Respective fail address bit values are stored in a plurality of fuses. A signal associated with a respective value of a portion of a further address is received. When the signal is received, one of the fail address bit values is delivered from one of the fuses to a corresponding latch circuit. The latch circuit receives fail address bit values from at least two of the fuses. One of the fail address bit values is selected based on the value associated with the signal. The latch circuit is activated to deliver the fail address bit value.

Abstract: Described are integrated circuit chips that are capable of self-adjusting an internal voltage of the integrated circuit chip and methods for adjusting the internal voltage of an integrated circuit chip. The methods include comparing an internally generated voltage to an external target voltage.

Abstract: Address information representing failed elements in an array portion of a device is delivered. Respective fail address bit values are stored in a plurality of fuses. A signal associated with a respective value of a portion of a further address is received. When the signal is received, one of the fail address bit values is delivered from one of the fuses to a corresponding latch circuit. The latch circuit receives fail address bit values from at least two of the fuses. One of the fail address bit values is selected based on the value associated with the signal. The latch circuit is activated to deliver the fail address bit value.

Abstract: For a selection of semiconductor chips stacked on top of one another, the invention includes leading through selection contact points of one chip on a rear side thereof and connecting them to corresponding selection contact points of the other semiconductor chip. Programmable input amplifiers are programmed to be transmissive or blocking through fuses/antifuses so that selection signals applied to the selection contact points either activate or block functional elements only of one or only of the other semiconductor chip. As a result, simple stacking of identically prefabricated semiconductor chips is made possible.