Abstract: A semiconductor packaging arrangement, or module, includes a printed circuit board having an electrical interconnect thereon and a semiconductor package mounted to the printed circuit board. The semiconductor package includes a fractional portion of a semiconductor wafer having a plurality of integrated circuit chips thereon, such chips being separated by regions in the fractional portion of the wafer. The fractional portion of the wafer has a plurality of electrical contacts electrically connected to the chips. The package also includes a dielectric member having an electrical conductor thereon. The electrical conductor are electrically connected to the plurality of electrical contacts of the plurality of chips to electrically interconnect such plurality of chips with portions of the electrical conductor spanning the regions in the fractional portion of the wafer.

Abstract: A semiconductor component that is suitable for wafer level packaging contains a plurality of contact elements that are elevated relative to a main body of the semiconductor component. Some of the contact elements are needed only for purposes of testing on the wafer level and should not be subsequently accessible from outside. For this purpose, the semiconductor component contains an insulating layer that covers the elevated contact elements that are provided for testing purposes but leaves the remaining contact elements uncovered. In this way, inadvertent activating of test functions on the chip is effectively prevented by simple measures, for instance by inserting only one additional fabrication step.

Abstract: Assessing the burn-in of faulty memory units on a wafer includes detecting only those defective memory cells that lie along control lines in the case of which the total number of defective memory cells does not exceed a predetermined limit value. With such a quality criterion, it is also possible to monitor the burn-in of faulty memory units on a wafer.

Abstract: An electronic component has a plurality of chips which are stacked one above the other and contact-connected to one another. To form this component, a first planar chip arrangement is provided with the functional chips spaced apart from one another in a grid and with a filling material in the spaces between the chips to form an insulating holding frame that fixes the chips, the frame has chip-dedicated contact-connecting elements that serve for the electrical contact-connection to another chip of another chip arrangement and each chip has dedicated electrically conductive strips. At least one additional planar chip arrangement is formed by the same method as the first planar chip arrangement and is then stacked on the first planar chip arrangement so that the two chip arrangements lie one above the other and the respective contact-connecting elements of the two chip arrangements are connected to one another for electrical chip-to-chip contact-connection.

Abstract: Circuitry using fuse and anti-fuse latches (62) for selecting the number of input/output channels (98, 109) after encapsulation is disclosed. The various embodiments allow conventional bond pads (14, 16, 18) to be used for initial selection of the number of input/output channels prior to encapsulation. However, by providing different selection signals (52, 54), the number of input/output channels may be changed by the user at any time after encapsulation. Other embodiments employ “enable” latch circuits (133,135) allow the initial selection by the users at any time after encapsulation, and then at least one more subsequent selection.

Abstract: In order to test, in parallel, semiconductor chips formed on a wafer, functionally identical contact points of the semiconductor chips are connected to column lines, and the rows of the semiconductor chips are selected by selection signal lines. This method is suitable in particular for checking electrically conductive connections between contact points of the semiconductor chips and mating contacts of a test head.

Abstract: A method of attaching semiconductor devices, the contact devices of which have preferably already been applied at wafer level, on a switching device and such a device includes having the electrical contacts remain free of solder by using flexible contact elements, and performing the mechanical attachment by additional attachment elements or compression stops used as attachment elements.

Abstract: A test socket for a semiconductor device includes a guide plate operable to receive the semiconductor device and to maintain electrical terminals of the semiconductor device in registration with electrical terminals of a base, a shell operable to couple to the base and to maintain the guide plate in registration with the electrical terminals of the base, the shell including an aperture in communication with the base through which the guide plate can be inserted and removed when the shell is coupled to the base; and at least one fastener coupled to the shell and operable to maintain the semiconductor device in engagement with the guide plate and to urge the electrical terminals of the semiconductor device in contact with the electrical terminals of the base. A method for operating the test socket is also disclosed.

Abstract: An apparatus for testing a plurality of semiconductor devices of a common wafer includes a plurality of driver circuits, each operable to produce an intermediate test signal as a function of a source test signal; a plurality of sets of isolation components, each isolation component of a given set (i) receiving the intermediate test signal from one of the driver circuits associated with the set, and (ii) producing a wafer level test signal such that each wafer level test signal is at least partially electrically isolated from one another; and a plurality of wafer contactors, each coupled to a respective one of the isolation components and operable to electrically connect to one of the semiconductor devices and to conduct a respective one of the wafer level test signals to that semiconductor device, wherein the wafer contactors are coupled to the isolation components such that adjacent semiconductor devices of the wafer receive wafer level test signals from different sets of isolation components.

Abstract: A semiconductor memory chip in accordance with the present invention includes a first memory array to be tested including a plurality of memory cells arranged in rows and columns, the memory cells being accessed to read and write data thereto by employing bitlines and wordlines, the data provided on input/output pins, and a pattern generator formed on the memory chip. The pattern generator further includes a programmable memory array including a plurality of memory banks, the memory banks having memory cells arranged in rows and columns, each bank being capable of storing data for a pattern to be generated for each of the input/output pins of the first memory array. An addressing circuit for accessing the data stored in the programmable memory array to address individual data to be transmitted to and from the first memory array is included.

Abstract: In a semiconductor chip, conductive tracks run in a rewiring layer from contact pads to contact elevations. The contact pads are formed as vias. The conductive tracks are constructed in sections as bottom electrodes of trimming capacitors. The top electrode of the trimming capacitors is formed by a metal plane of the rewiring layer.

Abstract: An apparatus for testing a plurality of semiconductor devices of a common wafer includes a plurality of driver circuits, each operable to produce an intermediate test signal as a function of a source test signal; a plurality of sets of isolation components, each isolation component of a given set (i) receiving the intermediate test signal from one of the driver circuits associated with the set, and (ii) producing a wafer level test signal such that each wafer level test signal is at least partially electrically isolated from one another; and a plurality of wafer contactors, each coupled to a respective one of the isolation components and operable to electrically connect to one of the semiconductor devices and to conduct a respective one of the wafer level test signals to that semiconductor device, wherein the wafer contactors are coupled to the isolation components such that adjacent semiconductor devices of the wafer receive wafer level test signals from different sets of isolation components.

Abstract: The present invention provides an apparatus for monitoring a state, in particular of a fuse (4), having: a first state storage device (11) for storing a state, in particular of a fuse (4); a second state storage device (12) for storing the state of the first state storage device (11); and a logic device (9) for comparing the states of the two state stores (11, 12); the first state store (11) being able to be driven for renewed reading in of the state, in particular of the fuse (4), in the event of a noncorrespondence of the states in the two stores (11, 12). The present invention likewise provides a method for monitoring a state, in particular of a fuse.

Abstract: A memory is provided having an array of rows and columns of memory cells. The memory includes plurality of sense amplifiers, each one having a true terminal and a compliment terminal. The memory also includes a plurality of pairs of twisted bit lines, each one of the pairs of lines being coupled to true and compliment terminals of a corresponding one of the plurality of sense amplifiers. A plurality of word lines is provided, each one being connected to a corresponding one of the rows of memory cells. An address logic section is fed by column address signals, fed to the bit lines, and row address signals, fed to the word lines, for producing invert/non-invert signals in accordance with the fed row and column address signals. The memory includes a plurality of inverters each one being coupled to a corresponding one of the sense amplifiers for inverting data fed to or read from the sense amplifier selectively in accordance with the invert/non-invert signals produced by the address logic.

Abstract: A circuit for refreshing data stored in an array of dynamic memory cells is provided. The circuit includes an integrated circuit chip. The chip has the array of memory cells formed thereon. The circuit also includes a refresh rate analysis circuit for determining data retention times in each one of the memory cells and from such determination refresh address modification signals. Also provided is a refresh address generator formed on the chip and fed by refresh command signals generated externally of the chip and by the address modification signals. The refresh address generator supplies an internal refresh commands along with refresh addresses to the array of memory cells. The cells have data stored therein refreshed in response to such internal refresh commands. The refresh rate analysis circuit determines cells in the array having data retention times less than a predetermined value.

Abstract: A circuit for refreshing data stored in an array of dynamic memory cells is provided. The circuit includes an integrated circuit chip. The chip has the array of memory cells formed thereon. The circuit also includes a refresh rate analysis circuit for determining data retention times in each one of the memory cells and from such determination refresh address modification signals. Also provided is a refresh address generator formed on the chip and fed by refresh command signals generated externally of the chip and by the address modification signals. The refresh address generator supplies an internal refresh commands along with refresh addresses to the array of memory cells. The cells have data stored therein refreshed in response to such internal refresh commands. The refresh rate analysis circuit determines cells in the array having data retention times less than a predetermined value.

Abstract: The invention provides a method for activating fuse units (101a-101n) in an electronic circuit device (100) in order to modify a circuit design for the electronic circuit device (100), where an electronic circuit device (100) in which fuse units (101a-101n) can be activated is selected, those fuse units (101a-101n) in the selected electronic circuit device (100) which can be activated in order to modify the circuit design for the electronic circuit device (100) are determined, the fuse units (101a-101n) which can be activated in order to mosdify the circuit design for the electronic circuit device (100) are addressed using fuse addressing units (102a-102n), and an activation state of the fuse units (101a-101n) which can be activated in order to modify the circuit design for the electronic circuit device (100) is stipulated, the fuse units (101a-101n) addressed using the fuse addressing units (102a-102n) being activated using fuse activation units (103a-103n) in line with the stipulated activation state.

Abstract: An automatic method for the generation of a logical hardware test pattern in memory circuits is based on a given physical pattern. The method includes backwards transformation from a given set of logical data patterns. Since the method is automatic, no knowledge of data scrambling inside the memory circuit is required.

Abstract: A memory is provided having an array of rows and columns of memory cells. The memory includes plurality of sense amplifiers, each one having a true terminal and a compliment terminal. The memory also includes a plurality of pairs of twisted bit lines, each one of the pairs of lines being coupled to true and compliment terminals of a corresponding one of the plurality of sense amplifiers. A plurality of word lines is provided, each one being connected to a corresponding one of the rows of memory cells. An address logic section is fed by column address signals, fed to the bit lines, and row address signals, fed to the word lines, for producing invert/non-invert signals in accordance with the fed row and column address signals. The memory includes a plurality of inverters each one being coupled to a corresponding one of the sense amplifiers for inverting data fed to or read from the sense amplifier selectively in accordance with the invert/non-invert signals produced by the address logic.

Abstract: An electronic component has a plurality of chips which are stacked one above the other and contact-connected to one another. To form this component, a first planar chip arrangement is provided with the functional chips spaced apart from one another in a grid and with a filling material in the spaces between the chips to form an insulating holding frame that fixes the chips, the frame has chip-dedicated contact-connecting elements that serve for the electrical contact-connection to another chip of another chip arrangement and each chip has dedicated electrically conductive strips. At least one additional planar chip arrangement is formed by the same method as the first planar chip arrangement and is then stacked on the first planar chip arrangement so that the two chip arrangements lie one above the other and the respective contact-connecting elements of the two chip arrangements are connected to one another for electrical chip-to-chip contact-connection.