Patents by Inventor Gerhard Prechtl

Gerhard Prechtl has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220344501
    Abstract: An enhancement mode Group III nitride-based transistor device includes a body having a first surface and a Group III nitride barrier layer arranged on a Group III nitride channel layer and forming a heterojunction therebetween. A first cell field includes transistor cells and an edge region. Each transistor cell includes source, gate and drain fingers extending substantially parallel to one another on the first surface in a longitudinal direction. The gate finger, arranged laterally between the source and drain fingers, includes a p-doped Group III nitride finger arranged between a metallic gate finger and the first surface. The edge region surrounds the transistor cells and includes an edge termination structure having an isolation ring and a p-doped Group III nitride runner. The isolation ring locally interrupts the heterojunction. The runner, extending transversely to the longitudinal direction, is located laterally between the isolation ring and an end of the drain finger.
    Type: Application
    Filed: July 7, 2022
    Publication date: October 27, 2022
    Inventors: Gerhard Prechtl, Gilberto Curatola, Oliver Haeberlen
  • Publication number: 20220271147
    Abstract: In an embodiment, a Group III nitride-based transistor device, includes a first Group III nitride barrier layer arranged on a Group III nitride channel layer, the first Group III nitride barrier layer and the Group III nitride channel layer having differing bandgaps and forming a heterojunction capable of supporting a two-dimensional charge gas. A source, a gate and a drain are on an upper surface of the first Group III nitride barrier layer. A gate recess extends from the upper surface of the first Group III nitride barrier layer into the first Group III nitride barrier layer. A p-doped Group III nitride material arranged in the gate recess has a first extension extending on the upper surface of the first Group III nitride barrier layer towards the drain. The first extension has a length ld, and 0 nm?ld?200 nm.
    Type: Application
    Filed: May 13, 2022
    Publication date: August 25, 2022
    Inventors: Clemens Ostermaier, Oliver Haeberlen, Gerhard Prechtl, Manuel Stabentheiner
  • Patent number: 11417758
    Abstract: An enhancement mode Group III nitride-based transistor device includes a body having a first surface and a Group III nitride barrier layer arranged on a Group III nitride channel layer and forming a heterojunction therebetween. A first cell field includes transistor cells and an edge region. Each transistor cell includes source, gate and drain fingers extending substantially parallel to one another on the first surface in a longitudinal direction. The gate finger, arranged laterally between the source and drain fingers, includes a p-doped Group III nitride finger arranged between a metallic gate finger and the first surface. The edge region surrounds the transistor cells and includes an edge termination structure having an isolation ring and a p-doped Group III nitride runner. The isolation ring locally interrupts the heterojunction. The runner, extending transversely to the longitudinal direction, is located laterally between the isolation ring and an end of the drain finger.
    Type: Grant
    Filed: August 10, 2020
    Date of Patent: August 16, 2022
    Assignee: Infineon Technologies Austria AG
    Inventors: Gerhard Prechtl, Gilberto Curatola, Oliver Haeberlen
  • Patent number: 11349012
    Abstract: In an embodiment, a Group III nitride-based transistor device, includes a first. Group III nitride barrier layer arranged on a Group III nitride channel layer, the first Group III nitride barrier layer and the Group III nitride channel layer having differing bandgaps and forming a heterojunction capable of supporting a two-dimensional charge gas. A source, a gate and a drain are on an upper surface of the first Group III nitride barrier layer. A gate recess extends from the upper surface of the first. Group III nitride barrier layer into the first Group III nitride barrier layer. A p-doped Group III nitride material arranged in the gate recess has a first extension extending on the upper surface of the first Group III nitride barrier layer towards the drain. The first extension has a length ld, and 0 nm?ld?200 nm.
    Type: Grant
    Filed: April 1, 2020
    Date of Patent: May 31, 2022
    Assignee: Infineon Technologies Austria AG
    Inventors: Clemens Ostermaier, Oliver Haeberlen, Gerhard Prechtl, Manuel Stabentheiner
  • Publication number: 20220123138
    Abstract: A method includes providing a semiconductor body including a plurality of two-dimensional charge carrier gas channels, forming a gate fin by forming a pair of gate trenches in an upper surface of the semiconductor body, the pair of gate trenches exposing each one of two-dimensional charge carrier gas channels, providing source and drain contacts that are electrically connected to each one of the plurality of two-dimensional charge carrier gas channels, providing a gate structure that is configured to control a conductive connection between the source and drain contacts, wherein providing the gate structure includes forming a layer of doped type III-nitride semiconductor material that covers the gate fin and extends into the gate trenches, and forming a conductive gate electrode on top of the layer of doped type III-nitride semiconductor material.
    Type: Application
    Filed: December 28, 2021
    Publication date: April 21, 2022
    Inventors: Thomas Detzel, Gerhard Prechtl, Oliver Haeberlen
  • Patent number: 11257941
    Abstract: A transistor device includes a gate fin that is a segment of a semiconductor body disposed between a pair of gate trenches formed in an upper surface of the semiconductor body, a plurality of two-dimensional charge carrier gas channels disposed at different vertical depths within the gate fin, source and drain contacts arranged on either side of the gate fin in a current flow direction of the gate fin, the source and drain contacts each being electrically connected to each one of the two-dimensional charge carrier gas channels, and a gate structure that is configured to control a conductive connection between the source and drain contacts. The gate structure includes a region of doped type III-nitride semiconductor material that covers the gate fin and extends into the gate trenches, and a conductive gate electrode formed over the region of doped type III-nitride semiconductor material.
    Type: Grant
    Filed: January 28, 2020
    Date of Patent: February 22, 2022
    Assignee: Infineon Technologies Austria AG
    Inventors: Thomas Detzel, Gerhard Prechtl, Oliver Haeberlen
  • Patent number: 11114554
    Abstract: A high-electron-mobility semiconductor device includes: a buffer region having first, second and third cross-sections forming a stepped lateral profile, the first cross-section being thicker than the third cross-section and comprising a first buried field plate disposed therein, the second cross-section interposed between the first and third cross-sections and forming oblique angles with the first and third cross-sections; and a barrier region of substantially uniform thickness extending along the stepped lateral profile of the buffer region, the barrier region being separated from the first buried field plate by a portion of the buffer region. The buffer region is formed by a first semiconductor material and the barrier region is formed by a second semiconductor material.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: September 7, 2021
    Assignee: Infineon Technologies Austria AG
    Inventors: Gerhard Prechtl, Clemens Ostermaier, Oliver Häberlen
  • Publication number: 20210234028
    Abstract: A transistor device includes a gate fin that is a segment of a semiconductor body disposed between a pair of gate trenches formed in an upper surface of the semiconductor body, a plurality of two-dimensional charge carrier gas channels disposed at different vertical depths within the gate fin, source and drain contacts arranged on either side of the gate fin in a current flow direction of the gate fin, the source and drain contacts each being electrically connected to each one of the two-dimensional charge carrier gas channels, and a gate structure that is configured to control a conductive connection between the source and drain contacts. The gate structure includes a region of doped type III-nitride semiconductor material that covers the gate fin and extends into the gate trenches, and a conductive gate electrode formed over the region of doped type III-nitride semiconductor material.
    Type: Application
    Filed: January 28, 2020
    Publication date: July 29, 2021
    Inventors: Thomas Detzel, Gerhard Prechtl, Oliver Haeberlen
  • Publication number: 20210050439
    Abstract: An enhancement mode Group III nitride-based transistor device includes a body having a first surface and a Group III nitride barrier layer arranged on a Group III nitride channel layer and forming a heterojunction therebetween. A first cell field includes transistor cells and an edge region. Each transistor cell includes source, gate and drain fingers extending substantially parallel to one another on the first surface in a longitudinal direction. The gate finger, arranged laterally between the source and drain fingers, includes a p-doped Group III nitride finger arranged between a metallic gate finger and the first surface. The edge region surrounds the transistor cells and includes an edge termination structure having an isolation ring and a p-doped Group III nitride runner. The isolation ring locally interrupts the heterojunction. The runner, extending transversely to the longitudinal direction, is located laterally between the isolation ring and an end of the drain finger.
    Type: Application
    Filed: August 10, 2020
    Publication date: February 18, 2021
    Inventors: Gerhard Prechtl, Gilberto Curatola, Oliver Haeberlen
  • Publication number: 20210050434
    Abstract: An integrated circuit includes a semiconductor substrate, first and second doping regions in the substrate, a first insulating layer on a first surface of the semiconductor substrate, the first insulating layer having first and second openings above the first and second doping regions, a polysilicon layer on the first insulating layer, the polysilicon layer having first and second openings above the first and second openings of the first insulating layer, a second insulating layer on the polysilicon layer and having first and second openings above the first and second openings of the polysilicon layer, a first contact element disposed in the first openings, a second contact element disposed in the second openings, the first and second contact elements being in contact with the first and second doping regions.
    Type: Application
    Filed: October 30, 2020
    Publication date: February 18, 2021
    Inventors: Gerhard Prechtl, Andreas Peter Meiser, Thomas Ostermann
  • Publication number: 20200321447
    Abstract: In an embodiment, a Group III nitride-based transistor device, includes a first. Group III nitride barrier layer arranged on a Group III nitride channel layer, the first Group III nitride barrier layer and the Group III nitride channel layer having differing bandgaps and forming a heterojunction. capable of supporting a two-dimensional charge gas. A source, a gate and a drain are on an upper surface of the first Group III nitride barrier layer. A gate recess extends from the upper surface of the first. Group III nitride barrier layer into the first Group III nitride barrier layer. A p-doped Group III nitride material arranged in the gate recess has a first extension extending on the upper surface of the first Group III nitride barrier layer towards the drain. The first extension has a length ld, and 0 nm?ld?200 nm.
    Type: Application
    Filed: April 1, 2020
    Publication date: October 8, 2020
    Inventors: Clemens Ostermaier, Oliver Haeberlen, Gerhard Prechtl, Manuel Stabentheiner
  • Patent number: 10600710
    Abstract: A semiconductor device includes a group III-semiconductor-nitride-based channel layer, a group III-semiconductor-nitride-based barrier layer formed on the channel layer, a two-dimensional electron gas channel formed in the channel layer, a first current electrode and a second current electrode formed on the barrier layer and laterally spaced from each other, and a gate structure formed on the barrier layer between the first and second current electrodes. The barrier layer has a symmetrically shaped recess between the first and second current electrodes, the symmetrically shaped recess including a first recess portion formed in a part of an upper surface of the barrier layer and a second recess portion formed within the first recess portion. The gate structure includes a group III-semiconductor-nitride-based doped layer that fills the symmetrically shaped recess and an electrically conductive gate electrode formed on an upper side of the doped layer that is opposite from the barrier layer.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: March 24, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Gerhard Prechtl, Clemens Ostermaier, Oliver Häberlen
  • Patent number: 10573568
    Abstract: A method of producing a semiconductor component is provided. The method includes providing a silicon substrate having a <111>-surface defining a vertical direction, forming in the silicon substrate at least one electronic component, forming at least two epitaxial semiconductor layers on the silicon substrate to form a heterojunction above the <111>-surface, and forming a HEMT-structure above the <111>-surface.
    Type: Grant
    Filed: September 6, 2017
    Date of Patent: February 25, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Gerhard Prechtl, Gebhart Dippold
  • Publication number: 20190326280
    Abstract: A semiconductor device includes a main bi-directional switch formed on a semiconductor substrate and having first and second gates, a first source electrically connected to a first voltage terminal, a second source electrically connected to a second voltage terminal, and a common drain. The semiconductor device further includes a discharge circuit having a plurality of individual transistors or an auxiliary bi-directional switch monolithically integrated with the main bi-directional switch and connected in a common source configuration to the semiconductor substrate. The plurality of individual transistors or the auxiliary bi-directional switch includes a first drain connected to the first source of the main bi-directional switch, a second drain connected to the second source of the main bi-directional switch, and first and second gates each decoupled from gate drive circuitry so that the first and the second gates are controlled at least passively and based on a state of the main bi-directional switch.
    Type: Application
    Filed: April 23, 2018
    Publication date: October 24, 2019
    Inventors: Mohamed Imam, Hyeongnam Kim, Kennith Kin Leong, Bhargav Pandya, Gerhard Prechtl
  • Patent number: 10411008
    Abstract: Circuits and devices for bidirectional normally-off switches are described. A circuit for a bidirectional normally-off switch includes a depletion mode transistor and an enhancement mode transistor. The depletion mode transistor includes a first source/drain node, a second source/drain node, a first gate, and a second gate. The enhancement mode transistor includes a third source/drain node and a fourth source/drain node, and a third gate. The third source/drain node is coupled to the first source/drain node.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: September 10, 2019
    Assignee: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventors: Gerhard Prechtl, Bernhard Zojer
  • Patent number: 10388736
    Abstract: In an embodiment, a method includes forming an intentionally doped superlattice laminate on a support substrate, forming a Group III nitride-based device having a heterojunction on the superlattice laminate layer, and forming a charge blocking layer between the heterojunction and the superlattice laminate.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: August 20, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Gerhard Prechtl, Horst Schäfer, Oliver Häberlen
  • Patent number: 10326441
    Abstract: A semiconductor assembly includes a first FET having gate, source and drain terminals, a switching device being configured to electrically short a gate-source capacitance of the first FET responsive to a control signal, a first gate lead, a second gate lead, a drain lead, and a source lead. The first and second gate leads, the drain lead, and the source lead form externally accessible terminals of the semiconductor assembly. A reverse blocking rating of the switching device is less than a reverse blocking rating of the first FET. A gate of the first FET is directly electrically connected to the first gate lead. A gate of the switching device is directly electrically connected to the second gate lead. The first FET and the switching device are the only active semiconductor devices connected between the first gate lead, the second gate lead, the drain lead, and the source lead.
    Type: Grant
    Filed: February 1, 2018
    Date of Patent: June 18, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Gerhard Prechtl, Severin Kampl
  • Patent number: 10304923
    Abstract: A method of manufacturing a semiconductor die includes forming a semiconductor body on a substrate. The semiconductor body has a periphery which is devoid of active devices and terminates at an edge face of the semiconductor die. The semiconductor body includes a first III-nitride semiconductor layer and a plurality of second III-nitride semiconductor layers below the first III-nitride semiconductor layer. The method further includes forming an uninsulated connection structure which extends vertically in the periphery of the semiconductor body and provides a vertical leakage path for at least some of the second III-nitride semiconductor layers either to the substrate or to a metallization layer disposed above the semiconductor body, but not to both. Additional semiconductor die manufacturing methods are provided.
    Type: Grant
    Filed: July 10, 2018
    Date of Patent: May 28, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Clemens Ostermaier, Gerhard Prechtl, Oliver Häberlen
  • Patent number: 10276669
    Abstract: A semiconductor device includes a base layer, a dielectric layer over the base layer, an opening extending through the dielectric layer and to a main surface of the base layer, the opening having a sloped sidewall, and an electrically conductive material over the sloped sidewall. An angle between the sloped sidewall and the main surface of the base layer is in a range between 5 degrees and 50 degrees. Corresponding methods of manufacturing the semiconductor device are also provided.
    Type: Grant
    Filed: January 19, 2017
    Date of Patent: April 30, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Jens Ulrich Heinle, Gerhard Prechtl, Gilberto Curatola
  • Publication number: 20190096779
    Abstract: A semiconductor device includes a group III-semiconductor-nitride-based channel layer, a group III-semiconductor-nitride-based barrier layer formed on the channel layer, a two-dimensional electron gas channel formed in the channel layer, a first current electrode and a second current electrode formed on the barrier layer and laterally spaced from each other, and a gate structure formed on the barrier layer between the first and second current electrodes. The barrier layer has a symmetrically shaped recess between the first and second current electrodes, the symmetrically shaped recess including a first recess portion formed in a part of an upper surface of the barrier layer and a second recess portion formed within the first recess portion. The gate structure includes a group III-semiconductor-nitride-based doped layer that fills the symmetrically shaped recess and an electrically conductive gate electrode formed on an upper side of the doped layer that is opposite from the barrier layer.
    Type: Application
    Filed: November 30, 2018
    Publication date: March 28, 2019
    Inventors: Gerhard Prechtl, Clemens Ostermaier, Oliver Häberlen