Abstract: A method includes providing a semiconductor body including a plurality of two-dimensional charge carrier gas channels, forming a gate fin by forming a pair of gate trenches in an upper surface of the semiconductor body, the pair of gate trenches exposing each one of two-dimensional charge carrier gas channels, providing source and drain contacts that are electrically connected to each one of the plurality of two-dimensional charge carrier gas channels, providing a gate structure that is configured to control a conductive connection between the source and drain contacts, wherein providing the gate structure includes forming a layer of doped type III-nitride semiconductor material that covers the gate fin and extends into the gate trenches, and forming a conductive gate electrode on top of the layer of doped type III-nitride semiconductor material.

Abstract: In an embodiment, a semiconductor device includes a Group III nitride-based substrate having a first major surface, a lateral Group III nitride-based device formed in the Group III nitride-based substrate, a first power contact and a second power contact arranged on the first major surface. At least one of the first power contact and the second power contact includes an electrode arranged on the first major surface, a field plate arranged on the electrode and having a lateral extent in a first direction parallel to the first major surface that is greater than a lateral extent of the electrode in the first direction, and a power metallic layer arranged directly on the field plate. The power metallic layer has a lateral extent in the first direction that is less than the lateral extent of the field plate in the first direction.

Abstract: A high-electron-mobility transistor comprises a semiconductor body comprising a barrier region and a channel region that forms a heterojunction with the barrier region such that a two-dimensional charge carrier gas channel is disposed in the channel region, source and drain electrodes disposed on the semiconductor body and laterally spaced apart from one another, a gate structure disposed on the semiconductor body and laterally between the source and drain electrodes, the gate structure being configured to control a conduction state of two-dimensional charge carrier gas, and a first dielectric region that is disposed along the upper surface of the semiconductor body in a lateral region that is between the gate structure and the drain electrode, wherein the first dielectric region comprises aluminum and oxide, and wherein first dielectric region comprises a first end that faces and is laterally spaced apart from the gate structure.

Abstract: A high-electron mobility transistor includes a semiconductor body including a barrier region, a channel region, and a two-dimensional charge carrier gas channel, first and second electrodes that are each in electrical contact with the two-dimensional charge carrier gas channel, and a gate structure laterally in between the first and second electrodes, wherein the gate structure comprises a gate electrode and a first region of doped type III-V semiconductor material in between the gate electrode and the two-dimensional charge carrier gas channel, wherein the first region of doped type III-V semiconductor material comprises a plurality of side faces that define a plan view geometry of the first region, and wherein in the plan view geometry of the first region at least two lateral boundaries of the first region that intersect one another extend along crystallographically equivalent planes of the doped type III-V semiconductor material.

Abstract: A high-electron-mobility transistor comprises a semiconductor body comprising a barrier region and a channel region that forms a heterojunction with the barrier region such that a two-dimensional charge carrier gas channel is disposed in the channel region, source and drain electrodes disposed on the semiconductor body and laterally spaced apart from one another, a gate structure disposed on the semiconductor body and laterally between the source and drain electrodes, the gate structure being configured to control a conduction state of two-dimensional charge carrier gas, and a first dielectric region that is disposed along the upper surface of the semiconductor body in a lateral region that is between the gate structure and the drain electrode, wherein the first dielectric region comprises aluminum and oxide, and wherein first dielectric region comprises a first end that faces and is laterally spaced apart from the gate structure.

Abstract: In an embodiment, a semiconductor die includes a base substrate having a first major surface, a second major surface opposing the first major surface, and a material other than a Group III nitride. A Group III nitride layer arranged on the first major surface of the base substrate includes a Group III nitride device. A first metallization structure is arranged on the Group III nitride layer and a second metallization structure is arranged on the second major surface of the base layer. The second metallization structure includes an electrically insulating inorganic layer arranged directly on the second major surface.

Abstract: In an embodiment, a Group III nitride-based transistor device, includes a first Group III nitride barrier layer arranged on a Group III nitride channel layer, the first Group III nitride barrier layer and the Group III nitride channel layer having differing bandgaps and forming a heterojunction capable of supporting a two-dimensional charge gas. A source, a gate and a drain are on an upper surface of the first Group III nitride barrier layer. A gate recess extends from the upper surface of the first Group III nitride barrier layer into the first Group III nitride barrier layer. A p-doped Group III nitride material arranged in the gate recess has a first extension extending on the upper surface of the first Group III nitride barrier layer towards the drain. The first extension has a length ld, and 0 nm?ld?200 nm.

Abstract: A method includes providing a semiconductor body including a plurality of two-dimensional charge carrier gas channels, forming a gate fin by forming a pair of gate trenches in an upper surface of the semiconductor body, the pair of gate trenches exposing each one of two-dimensional charge carrier gas channels, providing source and drain contacts that are electrically connected to each one of the plurality of two-dimensional charge carrier gas channels, providing a gate structure that is configured to control a conductive connection between the source and drain contacts, wherein providing the gate structure includes forming a layer of doped type III-nitride semiconductor material that covers the gate fin and extends into the gate trenches, and forming a conductive gate electrode on top of the layer of doped type III-nitride semiconductor material.

Abstract: A method includes providing a semiconductor body including a plurality of two-dimensional charge carrier gas channels, forming a gate fin by forming a pair of gate trenches in an upper surface of the semiconductor body, the pair of gate trenches exposing each one of two-dimensional charge carrier gas channels, providing source and drain contacts that are electrically connected to each one of the plurality of two-dimensional charge carrier gas channels, providing a gate structure that is configured to control a conductive connection between the source and drain contacts, wherein providing the gate structure includes forming a layer of doped type III-nitride semiconductor material that covers the gate fin and extends into the gate trenches, and forming a conductive gate electrode on top of the layer of doped type III-nitride semiconductor material.

Abstract: An electronic circuit and a method are disclosed. The electronic circuit includes: a first transistor device having a load path between a first load path node and a second load path node; and a clamping circuit connected to the load path of the first transistor device. The clamping circuit includes: a second transistor device having a load path connected in parallel with the load path of the first transistor device, and a control node; and a drive circuit configured to drive the second transistor device. The drive circuit includes a clamping element and a resistor connected in series between the first and second load path nodes of the first transistor device. The drive circuit is configured to drive the second transistor device dependent on a voltage across the resistor. The first transistor device and the clamping circuit are integrated in a same semiconductor die.

Abstract: In an embodiment, a semiconductor device is provided that includes a Group III nitride transistor device and a Schottky barrier diode integrated in a Group III nitride body. A common drain/cathode finger is arranged on the Group III nitride body. Two or more source contacts are arranged on the Group III nitride body and spaced apart in a row, the row being spaced laterally apart from, and extending substantially parallel to, the common drain/cathode finger. A gate electrode structure and one or more Schottky metal contacts are arranged on the Group III nitride body. At least one Schottky metal contact is arranged between and spaced apart from neighbouring ones of the source contacts. The gate electrode structure includes a closed ring section for each source contact that laterally surrounds that source contact. Neighbouring closed ring sections are connected by a gate connection section.

Abstract: A semiconductor device includes a main bi-directional switch formed on a semiconductor substrate and having first and second gates, a first source electrically connected to a first voltage terminal, a second source electrically connected to a second voltage terminal, and a common drain. The semiconductor device further includes a discharge circuit having a plurality of individual transistors or an auxiliary bi-directional switch monolithically integrated with the main bi-directional switch and connected in a common source configuration to the semiconductor substrate. The plurality of individual transistors or the auxiliary bi-directional switch includes a first drain connected to the first source of the main bi-directional switch, a second drain connected to the second source of the main bi-directional switch, and first and second gates each decoupled from gate drive circuitry so that the first and the second gates are controlled at least passively and based on a state of the main bi-directional switch.

Abstract: A high-electron-mobility transistor comprises a semiconductor body comprising a barrier region and a channel region that forms a heterojunction with the barrier region such that a two-dimensional charge carrier gas channel is disposed in the channel region, source and drain electrodes disposed on the semiconductor body and laterally spaced apart from one another, a gate structure disposed on the semiconductor body and laterally between the source and drain electrodes, the gate structure being configured to control a conduction state of two-dimensional charge carrier gas, and a first dielectric region that is disposed along the upper surface of the semiconductor body in a lateral region that is between the gate structure and the drain electrode, wherein the first dielectric region comprises aluminum and oxide, and wherein first dielectric region comprises a first end that faces and is laterally spaced apart from the gate structure.

Abstract: An enhancement mode Group III nitride-based transistor device includes a body having a first surface and a Group III nitride barrier layer arranged on a Group III nitride channel layer and forming a heterojunction therebetween. A first cell field includes transistor cells and an edge region. Each transistor cell includes source, gate and drain fingers extending substantially parallel to one another on the first surface in a longitudinal direction. The gate finger, arranged laterally between the source and drain fingers, includes a p-doped Group III nitride finger arranged between a metallic gate finger and the first surface. The edge region surrounds the transistor cells and includes an edge termination structure having an isolation ring and a p-doped Group III nitride runner. The isolation ring locally interrupts the heterojunction. The runner, extending transversely to the longitudinal direction, is located laterally between the isolation ring and an end of the drain finger.

Abstract: An enhancement mode Group III nitride-based transistor device includes a body having a first surface and a Group III nitride barrier layer arranged on a Group III nitride channel layer and forming a heterojunction therebetween. A first cell field includes transistor cells and an edge region. Each transistor cell includes source, gate and drain fingers extending substantially parallel to one another on the first surface in a longitudinal direction. The gate finger, arranged laterally between the source and drain fingers, includes a p-doped Group III nitride finger arranged between a metallic gate finger and the first surface. The edge region surrounds the transistor cells and includes an edge termination structure having an isolation ring and a p-doped Group III nitride runner. The isolation ring locally interrupts the heterojunction. The runner, extending transversely to the longitudinal direction, is located laterally between the isolation ring and an end of the drain finger.

Abstract: In an embodiment, a Group III nitride-based transistor device, includes a first Group III nitride barrier layer arranged on a Group III nitride channel layer, the first Group III nitride barrier layer and the Group III nitride channel layer having differing bandgaps and forming a heterojunction capable of supporting a two-dimensional charge gas. A source, a gate and a drain are on an upper surface of the first Group III nitride barrier layer. A gate recess extends from the upper surface of the first Group III nitride barrier layer into the first Group III nitride barrier layer. A p-doped Group III nitride material arranged in the gate recess has a first extension extending on the upper surface of the first Group III nitride barrier layer towards the drain. The first extension has a length ld, and 0 nm?ld?200 nm.

Abstract: An enhancement mode Group III nitride-based transistor device includes a body having a first surface and a Group III nitride barrier layer arranged on a Group III nitride channel layer and forming a heterojunction therebetween. A first cell field includes transistor cells and an edge region. Each transistor cell includes source, gate and drain fingers extending substantially parallel to one another on the first surface in a longitudinal direction. The gate finger, arranged laterally between the source and drain fingers, includes a p-doped Group III nitride finger arranged between a metallic gate finger and the first surface. The edge region surrounds the transistor cells and includes an edge termination structure having an isolation ring and a p-doped Group III nitride runner. The isolation ring locally interrupts the heterojunction. The runner, extending transversely to the longitudinal direction, is located laterally between the isolation ring and an end of the drain finger.

Abstract: In an embodiment, a Group III nitride-based transistor device, includes a first. Group III nitride barrier layer arranged on a Group III nitride channel layer, the first Group III nitride barrier layer and the Group III nitride channel layer having differing bandgaps and forming a heterojunction capable of supporting a two-dimensional charge gas. A source, a gate and a drain are on an upper surface of the first Group III nitride barrier layer. A gate recess extends from the upper surface of the first. Group III nitride barrier layer into the first Group III nitride barrier layer. A p-doped Group III nitride material arranged in the gate recess has a first extension extending on the upper surface of the first Group III nitride barrier layer towards the drain. The first extension has a length ld, and 0 nm?ld?200 nm.

Abstract: A method includes providing a semiconductor body including a plurality of two-dimensional charge carrier gas channels, forming a gate fin by forming a pair of gate trenches in an upper surface of the semiconductor body, the pair of gate trenches exposing each one of two-dimensional charge carrier gas channels, providing source and drain contacts that are electrically connected to each one of the plurality of two-dimensional charge carrier gas channels, providing a gate structure that is configured to control a conductive connection between the source and drain contacts, wherein providing the gate structure includes forming a layer of doped type III-nitride semiconductor material that covers the gate fin and extends into the gate trenches, and forming a conductive gate electrode on top of the layer of doped type III-nitride semiconductor material.

Abstract: A transistor device includes a gate fin that is a segment of a semiconductor body disposed between a pair of gate trenches formed in an upper surface of the semiconductor body, a plurality of two-dimensional charge carrier gas channels disposed at different vertical depths within the gate fin, source and drain contacts arranged on either side of the gate fin in a current flow direction of the gate fin, the source and drain contacts each being electrically connected to each one of the two-dimensional charge carrier gas channels, and a gate structure that is configured to control a conductive connection between the source and drain contacts. The gate structure includes a region of doped type III-nitride semiconductor material that covers the gate fin and extends into the gate trenches, and a conductive gate electrode formed over the region of doped type III-nitride semiconductor material.