Abstract: There are disclosed herein various implementations of a III-Nitride bidirectional device. Such a bidirectional device includes a substrate, a back channel layer situated over the substrate, and a device channel layer and a device barrier layer situated over the back channel layer. The device channel layer and the device barrier layer are configured to produce a device two-dimensional electron gas (2DEG). In addition, the III-Nitride bidirectional device includes first and second gates formed on respective first and second depletion segments situated over the device barrier layer. The III-Nitride bidirectional device also includes a back barrier situated between the back channel layer and the device channel layer. A polarization of the back channel layer of the III-Nitride bidirectional device is substantially equal to a polarization of the device channel layer.

Abstract: Circuits and devices for bidirectional normally-off switches are described. A circuit for a bidirectional normally-off switch includes a depletion mode transistor and an enhancement mode transistor. The depletion mode transistor includes a first source/drain node, a second source/drain node, a first gate, and a second gate. The enhancement mode transistor includes a third source/drain node and a fourth source/drain node, and a third gate. The third source/drain node is coupled to the first source/drain node.

Abstract: In an embodiment, a semiconductor device includes a Group III-nitride-based High Electron Mobility Transistor (HEMT) configured as a bidirectional switch. The Group III nitride-based HEMT includes a first input/output electrode, a second input/output electrode, a gate structure arranged between the first input/output electrode and the second input/output electrode, and a field plate structure.

Abstract: In an embodiment, a switch circuit includes a bidirectional switch including a first input/output node, a second input/output node, a first diode and a second diode. The first diode and the second diode are coupled anti-serially between the first input/output node and the second input/output node.

Abstract: In an embodiment, a semiconductor device includes a lateral transistor device having an upper metallization layer. The upper metallization layer includes n elongated pad regions. Adjacent ones of the n elongated pad regions are coupled to different current electrodes of the lateral transistor device. The n elongated pad regions bound n?1 active regions of the lateral transistor where n?3.

Abstract: A semiconductor device includes an III-V semiconductor body, a device formed in the III-V semiconductor body, one or more metal layers above the III-V semiconductor body, an interlayer dielectric adjacent each metal layer, a plurality of vias electrically connecting each metal layer to the device formed in the III-V semiconductor body, and a barrier disposed below the uppermost metal layer and in or above the lowermost interlayer dielectric. The barrier is configured to prevent water, water ions, sodium ions and potassium ions from diffusing into the interlayer dielectric or portion of the interlayer dielectric immediately below the barrier. Methods of manufacturing the semiconductor device are also provided.

Abstract: In an embodiment, an electronic device includes a semiconductor layer having a surface, a gate and a first current electrode on the surface and a dielectric layer extending between the gate and the first current electrode and including charged ions having a predetermined charge profile.

Abstract: A metalization of a field effect power transistor having lateral semiconductor layers on an insulator substrate or an intrinsically conducting or doped semiconductor substrate is provided. A metalization of source electrode contact areas, a metalization of drain electrode contact areas and a metalization of gate electrode contact areas are on a semiconductor surface of the semiconductor layers and have a plurality of metalization layers, between which insulation layers are arranged in a lateral direction. The metalization layers both for the source electrode metalization and for the drain electrode metalization have a comb structure with contact fingers. The contact fingers of the source electrode metalization and of the drain electrode metalization intermesh in a spaced-apart fashion and each contact finger has a contact finger foot and a contact finger tip. A width of the contact finger foot is greater than a width of the contact finger tip.

Abstract: A semiconductor component includes a semiconductor chip including a first semiconductor body comprising silicon and a second semiconductor body attached to an upper side of the first semiconductor body and comprising a III-nitride, and a lead-frame connected with the first semiconductor body. A thickness ratio between a thickness of the semiconductor chip and a thickness of the lead-frame is smaller than 1.3 or larger than 1.9.

Abstract: In an embodiment, a semiconductor device includes a High Electron Mobility Transistor (HEMT) including a floating gate. The floating gate includes two or more electrically separated floating gate segments.

Abstract: A substrate having a buffer layer and a barrier layer is formed. The buffer and barrier layers have different bandgaps such that an electrically conductive channel comprising a two-dimensional charge carrier gas arises at an interface between the buffer and barrier layers due to piezoelectric effects. The substrate is placed in a fluorine containing gas mixture that includes free radical state fluorine particles and is substantially devoid of ionic state fluorine particles. A first lateral surface section of the substrate is exposed to the gas mixture such that the free radical state fluorine particles contact the first lateral surface section without penetrating the substrate. A semiconductor device that incorporates first lateral surface section in the structure of the device is formed in the substrate.

Abstract: A semiconductor device is disclosed. One embodiment includes a lateral HEMT (High Electron Mobility Transistor) structure with a heterojunction between two differing group III-nitride semiconductor compounds and a layer arranged on the heterojunction. The layer includes a group III-nitride semiconductor compound and at least one barrier to hinder current flow in the layer.

Abstract: A metalization of a field effect power transistor having lateral semiconductor layers on an insulator substrate or an intrinsically conducting or doped semiconductor substrate is provided. A metalization of source electrode contact areas, a metalization of drain electrode contact areas and a metalization of gate electrode contact areas are on a semiconductor surface of the semiconductor layers and have a plurality of metalization layers, between which insulation layers are arranged in a lateral direction. The metalization layers both for the source electrode metalization and for the drain electrode metalization have a comb structure with contact fingers. The contact fingers of the source electrode metalization and of the drain electrode metalization intermesh in a spaced-apart fashion and each contact finger has a contact finger foot and a contact finger tip. A width of the contact finger foot is greater than a width of the contact finger tip.

Abstract: A substrate having a buffer layer and a barrier layer is formed. The buffer and barrier layers have different bandgaps such that an electrically conductive channel comprising a two-dimensional charge carrier gas arises at an interface between the buffer and barrier layers due to piezoelectric effects. The substrate is placed in a fluorine containing gas mixture that includes free radical state fluorine particles and is substantially devoid of ionic state fluorine particles. A first lateral surface section of the substrate is exposed to the gas mixture such that the free radical state fluorine particles contact the first lateral surface section without penetrating the substrate. A semiconductor device that incorporates first lateral surface section in the structure of the device is formed in the substrate.

Abstract: A Group III-nitride-based enhancement mode transistor includes a multi-heterojunction fin structure. A first side face of the multi-heterojunction fin structure is covered by a first p-type Group III-nitride layer, and a second side face of the multi-heterojunction fin structure is covered by a second p-type Group III-nitride layer.

Abstract: In an embodiment, a semiconductor device includes a substrate, a Group III nitride-based semiconductor layer formed on the substrate, a first current electrode and a second current electrode formed on the Group III nitride-based semiconductor layer and spaced from each other, and a control electrode formed on the Group III nitride-based semiconductor layer between the first current electrode and the second current electrode. The control electrode includes at least a middle portion, configured to switch off a channel below the middle portion when a first voltage is applied to the control electrode, and second portions adjoining the middle portion. The second portions are configured to switch off a channel below the second portions when a second voltage is applied to the control electrode, the second voltage being less than the first voltage and the second voltage being less than a threshold voltage of the second portions.

Abstract: A method of manufacturing a transistor device includes forming a compound semiconductor material on a semiconductor carrier, forming a source region and a drain region spaced apart from each other in the compound semiconductor material with a channel region interposed between the source and drain regions, forming a Schottky diode integrated with the semiconductor carrier, and forming contacts extending from the source and drain regions through the compound semiconductor material and in electrical contact with the Schottky diode so that the Schottky diode is connected in parallel between the source and drain regions.

Abstract: In an embodiment, a semiconductor device includes a High Electron Mobility Transistor (HEMT) including a floating gate. The floating gate includes two or more electrically separated floating gate segments.

Abstract: A semiconductor device includes a compound semiconductor material on a semiconductor substrate, the compound semiconductor material having a channel region, a source region, a drain region spaced apart from the source region, the channel region extending between the source region and the drain region, and an insulating region positioned under the channel region in an active region of the semiconductor device so that the insulating region is separated from the channel region by a portion of the compound semiconductor material in the active region. The active region includes the source, the drain and the channel region.

Abstract: A metalization of a field effect power transistor having lateral semiconductor layers on an insulator substrate or an intrinsically conducting semiconductor substrate is described. The lateral semiconductor layers have different band gaps such that a two-dimensional electron gas can form in their semiconductor depletion layer. Upon application of a voltage between source electrode contact areas and drain electrode contact areas or source and drain, an electric current can flow through the lateral semiconductor depletion layer. Current intensity in a channel region between the source electrode contact areas and the drain electrode contact areas is controllable via gate electrode contact areas by means of a gate voltage.