Abstract: A method of manufacturing a transistor device includes forming a semiconductor heterostructure including a plurality of alternating two-dimensional electron gasses (2DEGs) and two-dimensional hole gasses (2DHGs) extending in parallel at different depths in the semiconductor heterostructure, the 2DEGs forming current channels of the transistor device, forming a source extending into the semiconductor heterostructure in contact with the 2DEGs at a first end of the current channels, forming a drain extending into the semiconductor heterostructure in contact with the 2DEGs at an opposing second end of the current channels, and forming a plurality of spaced apart gate structures extending into the semiconductor heterostructure and including an electrically conductive material separated from the surrounding semiconductor heterostructure by an insulating material.

Abstract: A Group III-nitride-based enhancement mode transistor includes a multi-heterojunction fin structure. A first side face of the multi-heterojunction fin structure is covered by a p-type Group III-nitride layer.

Abstract: In an embodiment, a semiconductor device includes a lateral transistor device having an upper metallization layer. The upper metallization layer includes n elongated pad regions. Adjacent ones of the n elongated pad regions are coupled to different current electrodes of the lateral transistor device. The n elongated pad regions bound n-1 active regions of the lateral transistor where n?3.

Abstract: A metalization of a field effect power transistor having lateral semiconductor layers on an insulator substrate or an intrinsically conducting semiconductor substrate is described. The lateral semiconductor layers have different band gaps such that a two-dimensional electron gas can form in their semiconductor depletion layer. Upon application of a voltage between source electrode contact areas and drain electrode contact areas or source and drain, an electric current can flow through the lateral semiconductor depletion layer. Current intensity in a channel region between the source electrode contact areas and the drain electrode contact areas is controllable via gate electrode contact areas by means of a gate voltage.

Abstract: A normally-off compound semiconductor device includes a first III-nitride semiconductor having a first sloped transition region in which the first III-nitride semiconductor transitions at an angle from a first level to a second level different than the first level, and a second III-nitride semiconductor on the first III-nitride semiconductor and having a different band gap than the first III-nitride semiconductor so that a two-dimensional charge carrier gas arises along an interface between the first and second III-nitride semiconductors. The normally-off compound semiconductor device further includes a gate on the second III-nitride semiconductor and a doped semiconductor over the first sloped transition region and interposed between the gate and the second III-nitride semiconductor. The two-dimensional charge carrier gas is disrupted along the first sloped transition region due solely to the slope of the first sloped transition region if steep enough, or also due to the presence of the doped semiconductor.

Abstract: A high-electron-mobility field effect transistor is formed with a buffer region having a stepped lateral profile, the stepped lateral profile having first, second and third cross-sections of the buffer region, the first cross-section being thicker than the third cross-section and including a buried field plate, the second cross-section interposed between the first and third cross-sections and forming oblique angles with the first and third cross-sections. A barrier region is formed along the stepped lateral profile. The barrier region is separated from the buried field plate by a portion of the buffer region. The buffer region is formed from a first semiconductor material and the barrier region is formed from a second semiconductor material. The first and second semiconductor materials have different band-gaps such that an electrically conductive channel of a two-dimensional charge carrier gas arises at an interface between the buffer and barrier regions.

Abstract: An enhancement mode device includes a floating gate structure. The floating gate structure includes a first bottom dielectric layer, a second bottom dielectric layer on the first bottom dielectric layer and a conductive floating gate on the second bottom dielectric layer.

Abstract: A method of manufacturing a semiconductor device includes forming a semiconductor body including a compound semiconductor material on a substrate, the compound semiconductor material having a channel region, forming a source region extending to the compound semiconductor material, forming a drain region extending to the compound semiconductor material and spaced apart from the source region by the channel region, and forming an insulating region buried in the semiconductor body below the channel region between the compound semiconductor material and the substrate in an active region of the semiconductor device such that the channel region is uninterrupted by the insulating region. The active region includes the source, the drain and the channel region. The insulating region is discontinuous over a length of the channel region between the source region and the drain region.

Abstract: A method of manufacturing a semiconductor device includes forming a semiconductor body including a compound semiconductor material on a substrate, the compound semiconductor material having a channel region, forming a source region extending to the compound semiconductor material, forming a drain region extending to the compound semiconductor material and spaced apart from the source region by the channel region, and forming an insulating region buried in the semiconductor body below the channel region between the compound semiconductor material and the substrate in an active region of the semiconductor device such that the channel region is uninterrupted by the insulating region. The active region includes the source, the drain and the channel region. The insulating region is discontinuous over a length of the channel region between the source region and the drain region.

Abstract: An embodiment of a cascaded diode having a breakdown voltage exceeding 300V includes an HEMT and a Si Schottky diode. The HEMT includes a gate, a drain, a source, and a two-dimensional electron gas channel region connecting the source and the drain and controlled by the gate. The HEMT has a breakdown voltage exceeding 300V. The Si Schottky diode is monolithically integrated with the HEMT. The Si Schottky diode includes a cathode connected to the source of the HEMT and an anode connected to the gate of the HEMT. The Si Schottky diode has a breakdown voltage less than 300V and a forward voltage less than or equal to 0.4V. The anode of the Si Schottky diode forms the anode of the cascaded diode and the drain of the HEMT forms the cathode of the cascaded diode.

Abstract: A Group III-nitride-based enhancement mode transistor having a heterojunction fin structure and a corresponding semiconductor device are described.

Abstract: A Group III-nitride-based enhancement mode transistor includes a multi-heterojunction fin structure. A first side face of the multi-heterojunction fin structure is covered by a p-type Group III-nitride layer.

Abstract: A method of manufacturing a transistor device includes forming a semiconductor heterostructure including a plurality of alternating two-dimensional electron gasses (2DEGs) and two-dimensional hole gasses (2DHGs) extending in parallel at different depths in the semiconductor heterostructure, the 2DEGs forming current channels of the transistor device, forming a source extending into the semiconductor heterostructure in contact with the 2DEGs at a first end of the current channels, forming a drain extending into the semiconductor heterostructure in contact with the 2DEGs at an opposing second end of the current channels, and forming a plurality of spaced apart gate structures extending into the semiconductor heterostructure and including an electrically conductive material separated from the surrounding semiconductor heterostructure by an insulating material.

Abstract: An enhancement mode device includes a floating gate structure. The floating gate structure includes a first bottom dielectric layer, a second bottom dielectric layer on the first bottom dielectric layer and a conductive floating gate on the second bottom dielectric layer.

Abstract: A semiconductor device includes a semiconductor body having a compound semiconductor material on a substrate. The compound semiconductor material has a channel region. A source region extends to the compound semiconductor material. A drain region also extends to the compound semiconductor material and is spaced apart from the source region by the channel region. An insulating region is buried in the semiconductor body between the compound semiconductor material and the substrate in an active region of the semiconductor device. The active region includes the source, the drain and the channel region of the device. The insulating region is discontinuous over a length of the channel region between the source region and the drain region.

Abstract: A Group III-nitride-based enhancement mode transistor includes a heterojunction fin structure. Side faces and a top face of the heterojunction fin structure are covered by a p-type Group III-nitride layer.

Abstract: A transistor device includes a semiconductor heterostructure including a plurality of alternating two-dimensional electron gasses (2DEGs) and two-dimensional hole gasses (2DHGs) extending in parallel at different depths in the semiconductor heterostructure. The 2DEGs form current channels of the transistor device. The transistor device further includes a source extending into the semiconductor heterostructure in contact with the 2DEGs at a first end of the current channels, and a drain extending into the semiconductor heterostructure in contact with the 2DEGs at an opposing second end of the current channels. The transistor device also includes a plurality of spaced apart gate structures extending into the semiconductor heterostructure and including an electrically conductive material separated from the surrounding semiconductor heterostructure by an insulating material.

Abstract: In an embodiment, an electronic device includes a semiconductor layer having a surface, a gate and a first current electrode on the surface and a dielectric layer extending between the gate and the first current electrode and including charged ions having a predetermined charge profile.

Abstract: A semiconductor device is disclosed. One embodiment includes a lateral HEMT (High Electron Mobility Transistor) structure with a heterojunction between two differing group III-nitride semiconductor compounds and a layer arranged on the heterojunction. The layer includes a group III-nitride semiconductor compound and at least one barrier to hinder current flow in the layer.

Abstract: A semiconductor device is disclosed. One embodiment includes a lateral HEMT (High Electron Mobility Transistor) structure with a heterojunction between two differing group III-nitride semiconductor compounds and a layer arranged on the heterojunction. The layer includes a group III-nitride semiconductor compound and at least one barrier to hinder current flow in the layer.