Abstract: Circuits and devices for bidirectional normally-off switches are described. A circuit for a bidirectional normally-off switch includes a depletion mode transistor and an enhancement mode transistor. The depletion mode transistor includes a first source/drain node, a second source/drain node, a first gate, and a second gate. The enhancement mode transistor includes a third source/drain node and a fourth source/drain node, and a third gate. The third source/drain node is coupled to the first source/drain node.

Abstract: In an embodiment, a method includes forming an intentionally doped superlattice laminate on a support substrate, forming a Group III nitride-based device having a heterojunction on the superlattice laminate layer, and forming a charge blocking layer between the heterojunction and the superlattice laminate.

Abstract: A semiconductor assembly includes a first FET having gate, source and drain terminals, a switching device being configured to electrically short a gate-source capacitance of the first FET responsive to a control signal, a first gate lead, a second gate lead, a drain lead, and a source lead. The first and second gate leads, the drain lead, and the source lead form externally accessible terminals of the semiconductor assembly. A reverse blocking rating of the switching device is less than a reverse blocking rating of the first FET. A gate of the first FET is directly electrically connected to the first gate lead. A gate of the switching device is directly electrically connected to the second gate lead. The first FET and the switching device are the only active semiconductor devices connected between the first gate lead, the second gate lead, the drain lead, and the source lead.

Abstract: A method of manufacturing a semiconductor die includes forming a semiconductor body on a substrate. The semiconductor body has a periphery which is devoid of active devices and terminates at an edge face of the semiconductor die. The semiconductor body includes a first III-nitride semiconductor layer and a plurality of second III-nitride semiconductor layers below the first III-nitride semiconductor layer. The method further includes forming an uninsulated connection structure which extends vertically in the periphery of the semiconductor body and provides a vertical leakage path for at least some of the second III-nitride semiconductor layers either to the substrate or to a metallization layer disposed above the semiconductor body, but not to both. Additional semiconductor die manufacturing methods are provided.

Abstract: A semiconductor device includes a base layer, a dielectric layer over the base layer, an opening extending through the dielectric layer and to a main surface of the base layer, the opening having a sloped sidewall, and an electrically conductive material over the sloped sidewall. An angle between the sloped sidewall and the main surface of the base layer is in a range between 5 degrees and 50 degrees. Corresponding methods of manufacturing the semiconductor device are also provided.

Abstract: A semiconductor device includes a group III-semiconductor-nitride-based channel layer, a group III-semiconductor-nitride-based barrier layer formed on the channel layer, a two-dimensional electron gas channel formed in the channel layer, a first current electrode and a second current electrode formed on the barrier layer and laterally spaced from each other, and a gate structure formed on the barrier layer between the first and second current electrodes. The barrier layer has a symmetrically shaped recess between the first and second current electrodes, the symmetrically shaped recess including a first recess portion formed in a part of an upper surface of the barrier layer and a second recess portion formed within the first recess portion. The gate structure includes a group III-semiconductor-nitride-based doped layer that fills the symmetrically shaped recess and an electrically conductive gate electrode formed on an upper side of the doped layer that is opposite from the barrier layer.

Abstract: In an embodiment, a method includes treating an edge region of a wafer including a substrate having an upper surface and one or more epitaxial Group III nitride layers arranged on the upper surface of the substrate, so as to remove material including at least one Group III element from the edge region.

Abstract: In an embodiment, a semiconductor device includes a substrate, a Group III nitride-based semiconductor layer formed on the substrate, a first current electrode and a second current electrode formed on the Group III nitride-based semiconductor layer and spaced from each other, and a control electrode formed on the Group III nitride-based semiconductor layer between the first current electrode and the second current electrode. The control electrode includes at least a middle portion, configured to switch off a channel below the middle portion when a first voltage is applied to the control electrode, and second portions adjoining the middle portion. The second portions are configured to switch off a channel below the second portions when a second voltage is applied to the control electrode, the second voltage being less than the first voltage and the second voltage being less than a threshold voltage of the second portions.

Abstract: A probe test card for testing semiconductor devices includes a printed circuit board, a pair of electrically conductive probes extending towards one another and protruding away from the printed circuit board with a gap being disposed between ends of the pair of electrically conductive probes, and a coil affixed to and electrically connected to the printed circuit board and disposed directly over the gap. The probe test card is configured to generate a magnetic flux in the gap between the ends of the pair of electrically conductive probes upon the application of a current through the coil.

Abstract: A method of manufacturing a semiconductor die includes forming a semiconductor body on a substrate. The semiconductor body has a periphery which is devoid of active devices and terminates at an edge face of the semiconductor die. The semiconductor body includes a first III-nitride semiconductor layer and a plurality of second III-nitride semiconductor layers below the first III-nitride semiconductor layer. The method further includes forming an uninsulated connection structure which extends vertically in the periphery of the semiconductor body and provides a vertical leakage path for at least some of the second III-nitride semiconductor layers either to the substrate or to a metallization layer disposed above the semiconductor body, but not to both. Additional semiconductor die manufacturing methods are provided.

Abstract: A probe test card for testing semiconductor devices includes a printed circuit board, a pair of electrically conductive probes extending towards one another and protruding away from the printed circuit board with a gap being disposed between ends of the pair of electrically conductive probes, and a coil affixed to and electrically connected to the printed circuit board and disposed directly over the gap. The probe test card is configured to generate a magnetic flux in the gap between the ends of the pair of electrically conductive probes upon the application of a current through the coil.

Abstract: A normally-off compound semiconductor device includes a first III-nitride semiconductor having a first sloped transition region in which the first III-nitride semiconductor transitions at an angle from a first level to a second level different than the first level, and a second III-nitride semiconductor on the first III-nitride semiconductor and having a different band gap than the first III-nitride semiconductor so that a two-dimensional charge carrier gas arises along an interface between the first and second III-nitride semiconductors. The normally-off compound semiconductor device further includes a gate on the second III-nitride semiconductor and a doped semiconductor over the first sloped transition region and interposed between the gate and the second III-nitride semiconductor. The two-dimensional charge carrier gas is disrupted along the first sloped transition region due solely to the slope of the first sloped transition region if steep enough, or also due to the presence of the doped semiconductor.

Abstract: The disclosure is directed to techniques to evenly distribute current in interdigited leadframes by decoupling current between interdigited pads. The leadframe may use a perpendicular structure between the leadframe conductive pads and the lead traces. The perpendicular structure provides a short path for the current to travel from electrode pad openings on a device to the lead traces carrying current to other portions of a circuit. The conductive pad may be parallel to the electrode pad opening to lower spreading resistance. In an example of a transistor, the transistor may have two or more electrode pads for every current carrying node. Therefore, several electrode pads may have the same node, such as the source or drain of the device. For example, two or more source pads may be connected though the leadframe to evenly distribute the current and decouple the current from a single transistor.

Abstract: A semiconductor component includes a semiconductor chip including a first semiconductor body comprising silicon and a second semiconductor body attached to an upper side of the first semiconductor body and comprising a III-nitride, and a lead-frame connected with the first semiconductor body. A thickness ratio between a thickness of the semiconductor chip and a thickness of the lead-frame is smaller than 1.3 or larger than 1.9.

Abstract: A semiconductor die includes an III-V semiconductor body having a periphery devoid of active devices, the periphery terminating at an edge face of the semiconductor die. The semiconductor die further includes a seal ring structure above the periphery of the III-V semiconductor body and a barrier. The barrier is disposed over the periphery of the III-V semiconductor body at least between the seal ring structure and the edge face of the semiconductor die. The barrier has a density which prevents water, water ions, sodium ions and potassium ions from diffusing through the barrier.

Abstract: Circuits and devices for bidirectional normally-off switches are described. A circuit for a bidirectional normally-off switch includes a depletion mode transistor and an enhancement mode transistor. The depletion mode transistor includes a first source/drain node, a second source/drain node, a first gate, and a second gate. The enhancement mode transistor includes a third source/drain node and a fourth source/drain node, and a third gate. The third source/drain node is coupled to the first source/drain node.

Abstract: A semiconductor die includes a substrate and a semiconductor body supported by the substrate and having a periphery which is devoid of active devices and terminates at an edge face of the semiconductor die. The semiconductor body includes a first III-nitride semiconductor layer and a plurality of second III-nitride semiconductor layers below the first III-nitride semiconductor layer. An uninsulated connection structure extends vertically in the periphery of the semiconductor body and provides a vertical leakage path for at least some of the second III-nitride semiconductor layers to the substrate, to a metallization layer disposed above the substrate, or to both. A corresponding method of manufacturing the semiconductor die is also described.

Abstract: A method includes providing a heterostructure body with a buffer region, and a barrier region disposed on the buffer region, and forming a gate structure for controlling the channel on the heterostructure body, the gate structure having a doped semiconductor region disposed on the heterostructure body, an interlayer disposed on the doped semiconductor region, and a gate electrode disposed on the interlayer. Forming the gate structure includes controlling a doping concentration of the doped semiconductor region such that a portion of the channel adjacent the gate structure is non-conductive at zero gate bias, and controlling electrical and geometrical characteristics of the interlayer based upon a relationship between the electrical and geometrical characteristics of the interlayer and corresponding effects on a static threshold voltage and a dynamic threshold voltage shift of the semiconductor device.

Abstract: The disclosure is directed to techniques to evenly distribute current in interdigited leadframes by decoupling current between interdigited pads. The leadframe may use a perpendicular structure between the leadframe conductive pads and the lead traces. The perpendicular structure provides a short path for the current to travel from electrode pad openings on a device to the lead traces carrying current to other portions of a circuit. The conductive pad may be parallel to the electrode pad opening to lower spreading resistance. In an example of a transistor, the transistor may have two or more electrode pads for every current carrying node. Therefore, several electrode pads may have the same node, such as the source or drain of the device. For example, two or more source pads may be connected though the leadframe to evenly distribute the current and decouple the current from a single transistor.

Abstract: A semiconductor device includes a base layer, a dielectric layer over the base layer, an opening extending through the dielectric layer and to a main surface of the base layer, the opening having a sloped sidewall, and an electrically conductive material over the sloped sidewall. An angle between the sloped sidewall and the main surface of the base layer is in a range between 5 degrees and 50 degrees. Corresponding methods of manufacturing the semiconductor device are also provided.