Abstract: III-N high voltage MOS capacitors and System on Chip (SoC) solutions integrating at least one III-N MOS capacitor capable of high breakdown voltages (BV) to implement high voltage and/or high power circuits. Breakdown voltages over 4V may be achieved avoiding any need to series couple capacitors in an RFIC and/or PMIC. In embodiments, depletion mode III-N capacitors including a GaN layer in which a two dimensional electron gas (2DEG) is formed at threshold voltages below 0V are monolithically integrated with group IV transistor architectures, such as planar and non-planar silicon CMOS transistor technologies. In embodiments, silicon substrates are etched to provide a (111) epitaxial growth surface over which a GaN layer and III-N barrier layer are formed. In embodiments, a high-K dielectric layer is deposited, and capacitor terminal contacts are made to the 2DEG and over the dielectric layer.

Abstract: An apparatus is provided which comprises: at least two switches in series between an input voltage node and a ground terminal; an inductor coupled between a mid-point of the at least two switches and an output terminal; a first circuitry to compare a current through the inductor with a threshold current, and to control one or both of the at least two switches, based at least in part on the comparison; and a second circuitry to randomly vary the threshold current over consecutive cycles of switching of the at least two switches.

Abstract: Some embodiments include apparatuses and methods of operating such apparatuses. One of the embodiments includes an input node to receive an input voltage, a circuit portion to generate first, second, and third voltages based on the input voltage, a comparator circuit to compare the first voltage with the second voltage to generate a first signal and to compare the first voltage with the third voltage to generate a second signal, and an output circuit to generate an output signal based on the first and second signals.

Abstract: Embodiments are generally directed to hybrid magnetic material structures for electronic devices and circuits. An embodiment of an inductor includes a first layer of magnetic film material applied on a substrate, one or more conductors placed on the first layer of magnetic film material, and a second layer of magnetic particles, wherein the magnetic particles are suspended in an insulating medium.

Abstract: Apparatuses and methods of current balancing, current sensing and phase balancing, offset cancellation, digital to analog current converter with monotonic output using binary coded input (without binary to thermometer decoder), compensator for a voltage regulator (VR), etc. are provided here. An apparatus is provided which comprises: a plurality of inductors coupled to a capacitor and a load; a plurality of bridges, each of which is coupled to a corresponding inductor from the plurality of inductors; and a plurality of current sensors, each of which is coupled to a bridge to sense current through a transistor of the bridge.

Abstract: Described is an apparatus having a non-linear control to manage power supply droop at an output of a voltage regulator. The apparatus comprises: a first inductor for coupling to a load; a capacitor, coupled to the first inductor, and for coupling to the load; a first high-side switch couple to the first inductor; a first low-side switch coupled to the first inductor; a bridge controller to control when to turn on and off the first high-side and first low-side switches; and a non-linear control (NLC) unit to monitor output voltage on the load, and to cause the bridge controller to turn on the first high-side switch and turn off the first low-side switch when a voltage droop is detected on the load.

Abstract: III-N high voltage MOS capacitors and System on Chip (SoC) solutions integrating at least one III-N MOS capacitor capable of high breakdown voltages (BV) to implement high voltage and/or high power circuits. Breakdown voltages over 4V may be achieved avoiding any need to series couple capacitors in an RFIC and/or PMIC. In embodiments, depletion mode III-N capacitors including a GaN layer in which a two dimensional electron gas (2DEG) is formed at threshold voltages below 0V are monolithically integrated with group IV transistor architectures, such as planar and non-planar silicon CMOS transistor technologies. In embodiments, silicon substrates are etched to provide a (111) epitaxial growth surface over which a GaN layer and III-N barrier layer are formed. In embodiments, a high-K dielectric layer is deposited, and capacitor terminal contacts are made to the 2DEG and over the dielectric layer.

Abstract: Described herein is an apparatus and system for generating a signal with phase angle configuration. The apparatus comprises an array of switch-resistors, each switch resistor to receive a control signal, wherein the array of switch-resistors to generate an output signal; and a circuit to configure phase angle of the output signal. The apparatus can be used for different package and inductor configurations. The apparatus provides flexibility to mitigate switching noise by adjusting phase angles, and provides the ability to enable and disable switch-resistors on the fly without ripples. The apparatus also saves power consumption by selectively turning off switch-resistors when phases are disabled. The output signal of the apparatus has smooth triangular waveforms for improving the quality of power supply generated using the output signal. Overall, the apparatus exhibits reduced sensitivity to process variations compared to traditional signal generators.

Abstract: Described are apparatuses and methods of current balancing, current sensing and phase balancing, offset cancellation, digital to analog current converter with monotonic output using binary coded input (without binary to thermometer decoder), compensator for a voltage regulator (VR), etc. In one example, apparatus comprises: a plurality of inductors coupled to a capacitor and a load; a plurality of bridges, each of which is coupled to a corresponding inductor from the plurality of inductors; and a plurality of current sensors, each of which is coupled to a bridge to sense current through a transistor of the bridge.

Abstract: Described herein is an apparatus and system for generating a signal with phase angle configuration. The apparatus comprises an array of switch-resistors, each switch resistor to receive a control signal, wherein the array of switch-resistors to generate an output signal; and a circuit to configure phase angle of the output signal. The apparatus can be used for different package and inductor configurations. The apparatus provides flexibility to mitigate switching noise by adjusting phase angles, and provides the ability to enable and disable switch-resistors on the fly without ripples. The apparatus also saves power consumption by selectively turning off switch-resistors when phases are disabled. The output signal of the apparatus has smooth triangular waveforms for improving the quality of power supply generated using the output signal. Overall, the apparatus exhibits reduced sensitivity to process variations compared to traditional signal generators.

Abstract: III-N high voltage MOS capacitors and System on Chip (SoC) solutions integrating at least one III-N MOS capacitor capable of high breakdown voltages (BV) to implement high voltage and/or high power circuits. Breakdown voltages over 4V may be achieved avoiding any need to series couple capacitors in an RFIC and/or PMIC. In embodiments, depletion mode III-N capacitors including a GaN layer in which a two dimensional electron gas (2DEG) is formed at threshold voltages below 0V are monolithically integrated with group IV transistor architectures, such as planar and non-planar silicon CMOS transistor technologies. In embodiments, silicon substrates are etched to provide a (111) epitaxial growth surface over which a GaN layer and III-N barrier layer are formed. In embodiments, a high-K dielectric layer is deposited, and capacitor terminal contacts are made to the 2DEG and over the dielectric layer.

Abstract: The present disclosure provides a power delivery scheme to provide a parallel regulation feature for integrated voltage regulators (IVRs).

Abstract: An integrated circuit (IC) package is disclosed. The IC package includes a first die; and a second die bonded to the CPU die in a three dimensional packaging layout.

Abstract: A process of making inductors for integrated circuit packages may involve forming an inductor upon a magnetic film on a package substrate. Conductors coupled either to a die or a voltage converter extend perpendicularly through the film to conductive plates, defining current paths through and across the film.

Abstract: Described herein is a high-voltage level-shifter (HVLS) that can be used for both NMOS and PMOS bridges, exhibits a higher voltage tolerance for over-clocking than traditional level-shifters, has reduced crowbar current in its input driver, and no contention in its output driver. The HVLS comprises an input driver including a first signal conditioning unit, the input driver operating on a first power supply level and for conditioning an input signal as a first signal in the first signal conditioning unit; and a circuit to receive the first signal and to provide a second signal based at least in part on the first signal, the second signal being level-shifted from the first power supply level to a second power supply level, wherein the second power supply level is higher than the first power supply level.

Abstract: Described is an apparatus which comprises: a low-side switch coupled to an output node for providing regulated voltage supply; and a first driver operable to cause the low-side switch to turn off when the output node rises above a first transistor threshold voltage. Described is also a voltage regulator which comprises: a signal generator to generate a pulse-width modulated (PWM) signal; a bridge having a low-side switch coupled to an output node for providing regulated voltage supply according to the PWM signal; a first driver operable to cause the low-side switch to turn off when the output node rises above a first transistor threshold voltage; and a bridge controller to provide control signals to the first driver. The voltage regulator may operate without diode clamps and its operation is self-timed. The voltage regulator also provides tolerance against process variation.

Abstract: Described is an apparatus which comprises: a low-side switch coupled to an output node for providing regulated voltage supply; and a first driver operable to cause the low-side switch to turn off when the output node rises above a first transistor threshold voltage. Described is also a voltage regulator which comprises: a signal generator to generate a pulse-width modulated (PWM) signal; a bridge having a low-side switch coupled to an output node for providing regulated voltage supply according to the PWM signal; a first driver operable to cause the low-side switch to turn off when the output node rises above a first transistor threshold voltage; and a bridge controller to provide control signals to the first driver. The voltage regulator may operate without diode clamps and its operation is self-timed. The voltage regulator also provides tolerance against process variation.

Abstract: A method is described comprising conducting a first current through a switching transistor. The method also comprises conducting a second current through a pair of transistors whose conductive channels are coupled in series with respect to each other and are together coupled in parallel across the switching transistor's conductive channel. The second current is less than and proportional to the first current.

Abstract: III-N high voltage MOS capacitors and System on Chip (SoC) solutions integrating at least one III-N MOS capacitor capable of high breakdown voltages (BV) to implement high voltage and/or high power circuits. Breakdown voltages over 4V may be achieved avoiding any need to series couple capacitors in an RFIC and/or PMIC. In embodiments, depletion mode III-N capacitors including a GaN layer in which a two dimensional electron gas (2DEG) is formed at threshold voltages below 0V are monolithically integrated with group IV transistor architectures, such as planar and non-planar silicon CMOS transistor technologies. In embodiments, silicon substrates are etched to provide a (111) epitaxial growth surface over which a GaN layer and III-N barrier layer are formed. In embodiments, a high-K dielectric layer is deposited, and capacitor terminal contacts are made to the 2DEG and over the dielectric layer.

Abstract: Described is an apparatus for providing spread-spectrum to a clock signal. The apparatus comprises: an oscillator to generate an output clock signal, the oscillator to receive an adjustable reference signal to adjust frequency of the output clock signal; a first circuit to provide a first signal indicative of a center frequency of the output clock signal; a second circuit to generate a switching waveform to provide spread-spectrum for the output clock signal; and a third circuit, coupled to the first and second circuits, to provide the adjustable reference signal according to the first signal and the switching waveform.