Patents by Inventor Gerhard Schrom

Gerhard Schrom has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • INTEGRATED INDUCTORS
    Publication number: 20130182365
    Abstract: Multiple-inductor embodiments for use in substrates are provided herein.
    Type: Application
    Filed: February 4, 2013
    Publication date: July 18, 2013
    Inventors: Peter Hazucha, Trang T. Nguyen, Gerhard Schrom, Fabrice Paillet, Donald S. Gardner, Sung T. Moon, Tanay Karnik
  • DC-DC converter switching transistor current measurement technique
    Patent number: 8482552
    Abstract: A method is described comprising conducting a first current through a switching transistor. The method also comprises conducting a second current through a pair of transistors whose conductive channels are coupled in series with respect to each other and are together coupled in parallel across the switching transistor's conductive channel. The second current is less than and proportional to the first current.
    Type: Grant
    Filed: March 12, 2012
    Date of Patent: July 9, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Gerhard Schrom, Peter Hazucha, Vivek De, Tanay Karnik
  • On-die micro-transformer structures with magnetic materials
    Patent number: 8471667
    Abstract: Some embodiments include a die having a transformer. The transformer includes windings formed from a set of lines, such that no two lines belonging to any one winding are nearest neighbors. The lines are formed within one layer on the die. Other embodiments are described.
    Type: Grant
    Filed: November 29, 2010
    Date of Patent: June 25, 2013
    Assignee: Intel Corporation
    Inventors: Donald S. Gardner, Peter Hazucha, Gerhard Schrom
  • MULTIPHASE TRANSFORMER FOR A MULTIPHASE DC-DC CONVERTER
    Publication number: 20130113444
    Abstract: A multiphase DC-DC converter is provided that includes a multiphase transformer, the multiphase transformer including a plurality of input voltage terminals and an transformer output voltage terminal, each input voltage terminal associated with a corresponding phase. Each phase is assigned to an input voltage terminal of the plurality of input voltage terminals to minimize a ripple current at the input voltage terminals of the multiphase transformer.
    Type: Application
    Filed: December 26, 2012
    Publication date: May 9, 2013
    Inventors: Gerhard Schrom, Peter Hazucha, Jaeseo Lee, Tanay Karnik, Vivek K. De, Fabrice Paillet
  • Integrated inductor
    Patent number: 8373074
    Abstract: An inductor and multiple inductors embedded in a substrate (e.g., IC package substrate, board substrate, and/or other substrate) is provided herein.
    Type: Grant
    Filed: November 3, 2009
    Date of Patent: February 12, 2013
    Assignee: Intel Corporation
    Inventors: Peter Hazucha, Edward Burton, Trang T. Nguyen, Gerhard Schrom, Fabrice Paillet, Kaladhar Radhakrishnan, Donald S. Gardner, Sung T. Moon, Tanay Karnik
  • Integrated inductors
    Patent number: 8368501
    Abstract: Multiple-inductor embodiments for use in substrates are provided herein.
    Type: Grant
    Filed: June 29, 2006
    Date of Patent: February 5, 2013
    Assignee: Intel Corporation
    Inventors: Peter Hazucha, Trang T. Nguyen, Gerhard Schrom, Fabrice Paillet, Donald S. Gardner, Sung T. Moon, Tanay Karnik
  • Methods of forming magnetic vias to maximize inductance in integrated circuits and structures formed thereby
    Patent number: 8361594
    Abstract: Methods and associated structures of forming microelectronic devices are described. Those methods may include forming a first layer of a magnetic material on a substrate, forming an oxide layer on the first layer of the magnetic material, forming at least one conductive structure on the first magnetic layer, forming a dielectric layer on the at least one conductive structure, forming a second layer of the magnetic material on the at least one conductive structure, and forming a magnetic via coupled to the first and second layers of the magnetic material, wherein the magnetic via comprises a shape to increase inductance of the inductive structure.
    Type: Grant
    Filed: November 7, 2007
    Date of Patent: January 29, 2013
    Assignee: Intel Corporation
    Inventors: Donald Gardner, Gerhard Schrom, Peter Hazucha, Fabrice Paillet, Tanay Karnik
  • Multiphase transformer for a multiphase DC-DC converter
    Patent number: 8358112
    Abstract: A multiphase DC-DC converter is provided that includes a multiphase transformer, the multiphase transformer including a plurality of input voltage terminals and an transformer output voltage terminal, each input voltage terminal associated with a corresponding phase. Each phase is assigned to an input voltage terminal of the plurality of input voltage terminals to minimize a ripple current at the input voltage terminals of the multiphase transformer.
    Type: Grant
    Filed: March 16, 2009
    Date of Patent: January 22, 2013
    Assignee: Intel Corporation
    Inventors: Gerhard Schrom, Peter Hazucha, Jaeseo Lee, Fabrice Paillet, Tanay Karnik, Vivek De
  • Power management integrated circuit
    Patent number: 8288846
    Abstract: An integrated circuit (IC) package is disclosed. The IC package includes a first die; and a second die bonded to the CPU die in a three dimensional packaging layout.
    Type: Grant
    Filed: February 24, 2010
    Date of Patent: October 16, 2012
    Assignee: Intel Corporation
    Inventors: Siva G. Narendra, James W. Tschanz, Howard A. Wilson, Donald S. Gardner, Peter Hazucha, Gerhard Schrom, Tanay Karnik, Nitin Borkar, Vivek K. De, Shekhar Y. Borkar
  • PULSE WIDTH MODULATOR
    Publication number: 20120194245
    Abstract: Disclosed herein are pulse width modulator (PWM) solutions with comparators not relying on a variable reference to adjust duty cycle. In accordance with some embodiments, a pulse width modulator having a comparator with an applied adjustable waveform to generate a bit stream with a controllably adjustable duty cycle is provided.
    Type: Application
    Filed: February 24, 2012
    Publication date: August 2, 2012
    Inventors: Fabrice Paillet, Peter Hazucha, Gerhard Schrom, Tanay Karnik, Sung T. Moon, Donald S. Gardner
  • DC-DC CONVERTER SWITCHING TRANSISTOR CURRENT MEASUREMENT TECHNIQUE
    Publication number: 20120169425
    Abstract: A method is described comprising conducting a first current through a switching transistor. The method also comprises conducting a second current through a pair of transistors whose conductive channels are coupled in series with respect to each other and are together coupled in parallel across the switching transistor's conductive channel. The second current is less than and proportional to the first current.
    Type: Application
    Filed: March 12, 2012
    Publication date: July 5, 2012
    Inventors: Gerhard Schrom, Peter Hazucha, Vivek De, Tanay Karnik
  • Grounding of magnetic cores
    Patent number: 8198965
    Abstract: An apparatus includes a magnetic core, a ground node, and one or more vias to provide a connection between the magnetic core and the ground potential. The magnetic core includes a first magnetic layer and a second magnetic layer. In addition, the apparatus may include a conductive pattern. The conductive pattern may be at a third layer between the first and second magnetic layers. The apparatus may be included in inductors, transformers, transmission lines, and other components using ferromagnetic cores or shields. Such components may be integrated on a chip or die.
    Type: Grant
    Filed: November 4, 2010
    Date of Patent: June 12, 2012
    Assignee: Intel Corporation
    Inventors: Gerhard Schrom, Donald Gardner, Peter Hazucha, Fabrice Paillet, Tanay Karnik
  • DC-DC converter switching transistor current measurement technique
    Patent number: 8134548
    Abstract: A method is described comprising conducting a first current through a switching transistor. The method also comprises conducting a second current through a pair of transistors whose conductive channels are coupled in series with respect to each other and are together coupled in parallel across the switching transistor's conductive channel. The second current is less than and proportional to the first current.
    Type: Grant
    Filed: June 30, 2005
    Date of Patent: March 13, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Gerhard Schrom, Peter Hazucha, Vivek De, Tanay Karnik
  • Method for manufacturing integrated circuit inductors having slotted magnetic material
    Patent number: 8108984
    Abstract: Methods of manufacture of integrated circuit inductors having slotted magnetic material will be described. The methods may employ electro- or electroless plating techniques to form a layer or layers of magnetic material within the slotted magnetic material structure, and in particular those magnetic material layers adjacent to insulator layers.
    Type: Grant
    Filed: March 18, 2009
    Date of Patent: February 7, 2012
    Assignee: Intel Corporation
    Inventors: Donald S. Gardner, Gerhard Schrom, Peter Hazucha, Fabrice Paillet, Tanay Karnik
  • Inductors for Integrated Circuit Packages
    Publication number: 20110131797
    Abstract: An inductor may be formed from a magnetic film on a package substrate. Conductors coupled either to a die or a voltage converter extend perpendicularly through the film to conductive plates, defining current paths through and across the film.
    Type: Application
    Filed: February 14, 2011
    Publication date: June 9, 2011
    Inventors: Donald Gardner, Gerhard Schrom, Fabrice Paillet, Shamala Chickamenahalli
  • ON-DIE MICRO-TRANSFORMER STRUCTURES WITH MAGNETIC MATERIALS
    Publication number: 20110068887
    Abstract: Some embodiments include a die having a transformer. The transformer includes windings formed from a set of lines, such that no two lines belonging to any one winding are nearest neighbors. The lines are formed within one layer on the die. Other embodiments are described.
    Type: Application
    Filed: November 29, 2010
    Publication date: March 24, 2011
    Inventors: Donald S. Gardner, Peter Hazucha, Gerhard Schrom
  • Inductors for integrated circuit packages
    Patent number: 7911313
    Abstract: An inductor may be formed from a magnetic film on a package substrate. Conductors coupled either to a die or a voltage converter extend perpendicularly through the film to conductive plates, defining current paths through and across the film.
    Type: Grant
    Filed: July 2, 2008
    Date of Patent: March 22, 2011
    Assignee: Intel Corporation
    Inventors: Donald Gardner, Gerhard Schrom, Fabrice Paillet, Shamala Chickamenahalli
  • GROUNDING OF MAGNETIC CORES
    Publication number: 20110043318
    Abstract: An apparatus includes a magnetic core, a ground node, and one or more vias to provide a connection between the magnetic core and the ground potential. The magnetic core includes a first magnetic layer and a second magnetic layer. In addition, the apparatus may include a conductive pattern. The conductive pattern may be at a third layer between the first and second magnetic layers. The apparatus may be included in inductors, transformers, transmission lines, and other components using ferromagnetic cores or shields. Such components may be integrated on a chip or die.
    Type: Application
    Filed: November 4, 2010
    Publication date: February 24, 2011
    Inventors: GERHARD SCHROM, DONALD GARDNER, PETER HAZUCHA, FABRICE PAILLET, TANAY KARNIK
  • CMOS fabrication process utilizing special transistor orientation
    Patent number: 7888710
    Abstract: Complementary metal oxide semiconductor transistors are formed on a silicon substrate. The substrate has a {100} crystallographic orientation. The transistors are formed on the substrate so that current flows in the channels of the transistors are parallel to the <100> direction. Additionally, longitudinal tensile stress is applied to the channels.
    Type: Grant
    Filed: October 17, 2007
    Date of Patent: February 15, 2011
    Assignee: Intel Corporation
    Inventors: Mark Armstrong, Gerhard Schrom, Sunit Tyagi, Paul A. Packan, Kelin J. Kuhn, Scott Thompson
  • Forming inductor and transformer structures with magnetic materials using damascene processing for integrated circuits
    Patent number: 7867787
    Abstract: Methods and associated structures of forming microelectronic devices are described. Those methods may include forming a first layer of magnetic material and at least one via structure disposed in a first dielectric layer, forming a second dielectric layer disposed on the first magnetic layer, forming at least one conductive structure disposed in the second dielectric layer, forming a third layer of dielectric material disposed on the conductive structure, forming a second layer of magnetic material disposed in the third layer of dielectric material and in the second layer of dielectric material, wherein the first and second layers of the magnetic material are coupled to one another.
    Type: Grant
    Filed: December 31, 2007
    Date of Patent: January 11, 2011
    Assignee: Intel Corporation
    Inventors: Donald S. Gardner, Gerhard Schrom, Peter Hazucha, Fabrice Paillet, Tanay Karnik