Patents by Inventor Gerhard Schrom

Gerhard Schrom has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • FORMING INDUCTOR AND TRANSFORMER STRUCTURES WITH MAGNETIC MATERIALS USING DAMASCENE PROCESSING FOR INTEGRATED CIRCUITS
    Publication number: 20110001202
    Abstract: Methods and associated structures of forming microelectronic devices are described. Those methods may include forming a first layer of magnetic material and at least one via structure disposed in a first dielectric layer, forming a second dielectric layer disposed on the first magnetic layer, forming at least one conductive structure disposed in the second dielectric layer, forming a third layer of dielectric material disposed on the conductive structure, forming a second layer of magnetic material disposed in the third layer of dielectric material and in the second layer of dielectric material, wherein the first and second layers of the magnetic material are coupled to one another.
    Type: Application
    Filed: September 15, 2010
    Publication date: January 6, 2011
    Inventors: Donald S. Gardner, Gerhard Schrom, Peter Hazucha, Fabrice Paillet, Tanay Karnik
  • On-die micro-transformer structures with magnetic materials
    Patent number: 7852185
    Abstract: A transformer integrated on a die, the transformer comprising a set of conductive lines formed on the die within one layer and interconnected among each other so that no two lines belonging to any one winding are nearest neighbors. The set of conductive lines is surrounded by a magnetic material, which may be amorphous CoZrTa, CoFeHfO, CoAlO, FeSiO, CoFeAlO, CoNbTa, CoZr, and other amorphous cobalt alloys. The transformer may be operated at frequencies higher than 10 MHz and as high as 1 GHz, with relatively low resistance and relatively high magnetic coupling between the windings.
    Type: Grant
    Filed: May 5, 2003
    Date of Patent: December 14, 2010
    Assignee: Intel Corporation
    Inventors: Donald S. Gardner, Peter Hazucha, Gerhard Schrom
  • Grounding of magnetic cores
    Patent number: 7843304
    Abstract: An apparatus includes a magnetic core, a ground node, and one or more vias to provide a connection between the magnetic core and the ground potential. The magnetic core includes a first magnetic layer and a second magnetic layer. In addition, the apparatus may include a conductive pattern. The conductive pattern may be at a third layer between the first and second magnetic layers. The apparatus may be included in inductors, transformers, transmission lines, and other components using ferromagnetic cores or shields. Such components may be integrated on a chip or die.
    Type: Grant
    Filed: April 29, 2009
    Date of Patent: November 30, 2010
    Assignee: Intel Corporation
    Inventors: Gerhard Schrom, Donald Gardner, Peter Hazucha, Fabrice Paillet, Tanay Karnik
  • Power management integrated circuit
    Publication number: 20100219516
    Abstract: An integrated circuit (IC) package is disclosed. The IC package includes a first die; and a second die bonded to the CPU die in a three dimensional packaging layout.
    Type: Application
    Filed: February 24, 2010
    Publication date: September 2, 2010
    Inventors: Siva G. Narendra, James W. Tschanz, Howard A. Wilson, Donald S. Gardner, Peter Hazucha, Gerhard Schrom, Tanay Karnik, Nitin Borkar, Vivek K. De, Shekhar Y. Borkar
  • Laminated magnetic material for inductors in integrated circuits
    Patent number: 7719084
    Abstract: An embodiment is an inductor that may include a laminated material structure to decrease eddy currents therein that may limit the operation of the inductor at high frequency. An embodiment may employ electroless plating techniques to form a layer or layers of magnetic material within the laminated material structure, and in particular those magnetic layers adjacent to insulator layers.
    Type: Grant
    Filed: June 30, 2006
    Date of Patent: May 18, 2010
    Assignee: Intel Corporation
    Inventors: Donald S. Gardner, Gerhard Schrom, Peter Hazucha, Fabrice Paillet, Tanay Karnik
  • Integrated inductor
    Publication number: 20100118501
    Abstract: An inductor and multiple inductors embedded in a substrate (e.g., IC package substrate, board substrate, and/or other substrate) is provided herein.
    Type: Application
    Filed: November 3, 2009
    Publication date: May 13, 2010
    Inventors: Peter Hazucha, Edward Burton, Trang T. Nguyen, Gerhard Schrom, Fabrice Paillet, Kaladhar Radhakrishnan, Donald S. Gardner, Sung T. Moon, Tanay Karnik
  • CPU POWER DELIVERY SYSTEM
    Publication number: 20100115301
    Abstract: A central processing unit (CPU) is disclosed. The CPU includes a CPU die; and a voltage regulator die bonded to the CPU die in a three dimensional packaging layout.
    Type: Application
    Filed: January 8, 2010
    Publication date: May 6, 2010
    Inventors: Siva G. Narendra, Howard A. Wilson, Donald S. Gardner, Peter Hazucha, Gerhard Schrom, Tanay Karnik, Nitin Borkar, Vivek K. De, Shekhar Y. Borkar
  • Control of eddy currents in magnetic vias for inductors and transformers in integrated circuits
    Patent number: 7710234
    Abstract: An embodiment is a magnetic via. More specifically, an embodiment is a magnetic via that increases the inductance of, for example, an integrated inductor or transformer while mitigating eddy currents therein that may limit the operation of the inductor or transformer at high frequency.
    Type: Grant
    Filed: August 6, 2008
    Date of Patent: May 4, 2010
    Assignee: Intel Corporation
    Inventors: Donald S. Gardner, Gerhard Schrom, Peter Hazucha, Fabrice Paillet, Tanay Kamik
  • CPU power delivery system
    Patent number: 7698576
    Abstract: A central processing unit (CPU) is disclosed. The CPU includes a CPU die; and a voltage regulator die bonded to the CPU die in a three dimensional packaging layout.
    Type: Grant
    Filed: September 30, 2004
    Date of Patent: April 13, 2010
    Assignee: Intel Corporation
    Inventors: Siva G. Narendra, Howard A. Wilson, Donald S. Gardner, Peter Hazucha, Gerhard Schrom, Tanay Karnik, Nitin Borkar, Vivek K. De, Shekhar Y. Borkar
  • Power management integrated circuit
    Patent number: 7671456
    Abstract: An integrated circuit (IC) package is disclosed. The IC package includes a first die; and a second die bonded to the CPU die in a three dimensional packaging layout.
    Type: Grant
    Filed: July 3, 2007
    Date of Patent: March 2, 2010
    Assignee: Intel Corporation
    Inventors: Siva G. Narendra, James W. Tschantz, Howard A. Wilson, Donald S. Gardner, Peter Hazucha, Gerhard Schrom, Tanay Karnik, Nitin Borkar, Vivek K. De, Shekhar Y. Borkar
  • Inductors for integrated circuit packages
    Publication number: 20100001826
    Abstract: An inductor may be formed from a magnetic film on a package substrate. Conductors coupled either to a die or a voltage converter extend perpendicularly through the film to conductive plates, defining current paths through and across the film.
    Type: Application
    Filed: July 2, 2008
    Publication date: January 7, 2010
    Inventors: Donald Gardner, Gerhard Schrom, Fabrice Paillet, Shamala Chickamenahalli
  • Integrated inductor
    Patent number: 7636242
    Abstract: An inductor and multiple inductors embedded in a substrate (e.g., IC package substrate, board substrate, and/or other substrate) is provided herein.
    Type: Grant
    Filed: June 29, 2006
    Date of Patent: December 22, 2009
    Assignee: Intel Corporation
    Inventors: Peter Hazucha, Edward Burton, Trang T. Nguyen, Gerhard Schrom, Fabrice Paillet, Kaladhar Radhakrishnan, Donald S. Gardner, Sung T. Moon, Tanay Karnik
  • GROUNDING OF MAGNETIC CORES
    Publication number: 20090267722
    Abstract: An apparatus includes a magnetic core, a ground node, and one or more vias to provide a connection between the magnetic core and the ground potential. The magnetic core includes a first magnetic layer and a second magnetic layer. In addition, the apparatus may include a conductive pattern. The conductive pattern may be at a third layer between the first and second magnetic layers. The apparatus may be included in inductors, transformers, transmission lines, and other components using ferromagnetic cores or shields. Such components may be integrated on a chip or die.
    Type: Application
    Filed: April 29, 2009
    Publication date: October 29, 2009
    Inventors: GERHARD SCHROM, DONALD GARDNER, PETER HAZUCHA, FABRICE PAILLET, TANAY KARNIK
  • Signal generating circuit
    Patent number: 7602257
    Abstract: A signal generating circuit is provided. The signal generating circuit may include a plurality of delay circuits coupled to provide a plurality of control signals, a weighted-sum circuit to receive the plurality of control signals and to provide an output analog signal, and a comparator circuit to compare the output analog signal with a voltage and to provide a pulse width modulated (PWM) signal based on the comparison.
    Type: Grant
    Filed: December 19, 2006
    Date of Patent: October 13, 2009
    Assignee: Intel Corporation
    Inventors: Gerhard Schrom, Dinesh Somasekhar, Fabrice Paillet, Peter Hazucha, Sung Tae Moon, Tanay Karnik
  • SLOTTED MAGNETIC MATERIAL FOR INTEGRATED CIRCUIT INDUCTORS
    Publication number: 20090207576
    Abstract: An embodiment is an inductor that may include a slotted magnetic material to decrease eddy currents therein that may limit the operation of the inductor at high frequency. An embodiment may employ electro- or electroless plating techniques to form a layer or layers of magnetic material within the slotted magnetic material structure, and in particular those magnetic material layers adjacent to insulator layers.
    Type: Application
    Filed: March 18, 2009
    Publication date: August 20, 2009
    Applicant: INTEL CORPORATION
    Inventors: Donald S. Gardner, Gerhard Schrom, Peter Hazucha, Fabrice Paillet, Tanay Karnik
  • Power Delivery System
    Publication number: 20090199033
    Abstract: A system is disclosed. The system includes a load, a voltage regulator circuit coupled to the load a power supply, a load coupled to the power supply to receive one or more voltages from the power supply, and a digital bus, coupled between the power supply and the load. The digital bus transmits power consumption measurements from the load to the power supply and transmits power consumption measurements from the power supply to the load.
    Type: Application
    Filed: January 20, 2009
    Publication date: August 6, 2009
    Inventors: Shekhar Borkar, Tanay Karnik, Peter Hazucha, Gerhard Schrom, Greg Dermer
  • MULTIPHASE TRANSFORMER FOR A MULTIPHASE DC-DC CONVERTER
    Publication number: 20090174377
    Abstract: A multiphase DC-DC converter is provided that includes a multiphase transformer, the multiphase transformer including a plurality of input voltage terminals and an transformer output voltage terminal, each input voltage terminal associated with a corresponding phase. Each phase is assigned to an input voltage terminal of the plurality of input voltage terminals to minimize a ripple current at the input voltage terminals of the multiphase transformer.
    Type: Application
    Filed: March 16, 2009
    Publication date: July 9, 2009
    Inventors: Gerhard Schrom, Peter Hazucha, Jaeseo Lee, Fabrice Paillet, Tanay Karnik, Vivek De
  • FORMING INDUCTOR AND TRANSFORMER STRUCTURES WITH MAGNETIC MATERIALS USING DAMASCENE PROCESSING FOR INTEGRATED CIRCUITS
    Publication number: 20090166804
    Abstract: Methods and associated structures of forming microelectronic devices are described. Those methods may include forming a first layer of magnetic material and at least one via structure disposed in a first dielectric layer, forming a second dielectric layer disposed on the first magnetic layer, forming at least one conductive structure disposed in the second dielectric layer, forming a third layer of dielectric material disposed on the conductive structure, forming a second layer of magnetic material disposed in the third layer of dielectric material and in the second layer of dielectric material, wherein the first and second layers of the magnetic material are coupled to one another.
    Type: Application
    Filed: December 31, 2007
    Publication date: July 2, 2009
    Applicant: INTEL CORPORATION
    Inventors: Donald S. Gardner, Gerhard Schrom, Peter Hazucha, Fabrice Paillet, Tanay Karnik
  • Grounding of magnetic cores
    Patent number: 7538653
    Abstract: An apparatus includes a magnetic core, a ground node, and one or more vias to provide a connection between the magnetic core and the ground potential. The magnetic core includes a first magnetic layer and a second magnetic layer. In addition, the apparatus may include a conductive pattern. The conductive pattern may be at a third layer between the first and second magnetic layers. The apparatus may be included in inductors, transformers, transmission lines, and other components using ferromagnetic cores or shields. Such components may be integrated on a chip or die.
    Type: Grant
    Filed: March 30, 2007
    Date of Patent: May 26, 2009
    Assignee: Intel Corporation
    Inventors: Gerhard Schrom, Donald Gardner, Peter Hazucha, Fabrice Paillet, Tanay Karnik
  • METHODS OF FORMING MAGNETIC VIAS TO MAXIMIZE INDUCTANCE IN INTEGRATED CIRCUITS AND STRUCTURES FORMED THEREBY
    Publication number: 20090117325
    Abstract: Methods and associated structures of forming microelectronic devices are described. Those methods may include forming a first layer of a magnetic material on a substrate, forming an oxide layer on the first layer of the magnetic material, forming at least one conductive structure on the first magnetic layer, forming a dielectric layer on the at least one conductive structure, forming a second layer of the magnetic material on the at least one conductive structure, and forming a magnetic via coupled to the first and second layers of the magnetic material, wherein the magnetic via comprises a shape to increase inductance of the inductive structure.
    Type: Application
    Filed: November 7, 2007
    Publication date: May 7, 2009
    Inventors: Donald Gardner, Gerhard Schrom, Peter Hazucha, Fabrice Paillet, Tanay Karnik