Patents by Inventor Gerrit J. Leusink

Gerrit J. Leusink has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11908728
    Abstract: Techniques herein include a process chamber for depositing thin films to backside surfaces of wafers to reduce wafer bowing and distortion. A substrate support provides an annular perimeter seal around the bottom and/or side of the wafer which allows the majority of the substrate backside to be exposed to a process environment. A supported wafer separates the chamber into lower and upper chambers that provide different process environments. The lower section of the processing chamber includes deposition hardware configured to apply and remove thin films. The upper section can remain a chemically inert environment, protecting the existing features on the top surface of the wafer. Multiple exhausts and differential pressures are used to prevent deposition gasses from accessing the working surface of a wafer.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: February 20, 2024
    Assignee: Tokyo Electron Limited
    Inventors: Ronald Nasman, Gerrit J. Leusink, Rodney L. Robison, Hoyoung Kang, Daniel Fulford
  • Patent number: 11894240
    Abstract: A system for processing semiconductor wafers, the system including: a processing chamber; a heat source; a substrate holder configured to expose a semiconductor wafer to the heat source; a first electrode configured to be detachably coupled to a first major surface of a semiconductor wafer; and a second electrode coupled to the substrate holder, the first electrode and the second electrode together configured to apply an electric field in the semiconductor wafer.
    Type: Grant
    Filed: February 25, 2021
    Date of Patent: February 6, 2024
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: David Hurley, Ioan Domsa, Ian Colgan, Gerhardus Van Der Linde, Patrick Hughes, Maciej Burel, Barry Clarke, Mihaela Ioana Popovici, Lars-Ake Ragnarsson, Gerrit J. Leusink, Robert Clark, Dina Triyoso
  • Publication number: 20220301930
    Abstract: A method for filling recessed features with a low-resistivity metal. The method includes providing a patterned substrate containing a recessed feature formed in a first layer and a second layer that is exposed in the recessed feature, forming a nucleation enhancement layer on a sidewall of the first layer in the recessed feature and depositing a metal layer in the recessed feature by vapor phase deposition, where the metal layer is deposited on the second layer and on the nucleation enhancement layer. An initial metal layer may be selectively formed on the second layer in the recessed feature before forming the nucleation enhancement layer.
    Type: Application
    Filed: March 7, 2022
    Publication date: September 22, 2022
    Inventors: Kai-Hung Yu, Shihsheng Chang, Ying Trickett, Eric Chih-Fang Liu, Yun Han, Henan Zhang, Cory Wajda, Robert D. Clark, Gerrit J. Leusink, Gyanaranjan Pattanaik, Hiroaki Niimi
  • Patent number: 11444082
    Abstract: Aspects of the disclosure provide a method for forming a semiconductor apparatus. The method includes forming a first field-effect transistor (FET) that includes a first gate on a substrate of the semiconductor apparatus. The method includes forming a second FET that is stacked on the first FET along a direction substantially perpendicular to the substrate and includes a second gate. The method includes forming a first routing track and a second routing track that is electrically isolated from the first routing track. Each of the first and second routing tracks is provided on a routing plane stacked on the second FET along the direction. A first conductive trace configured to conductively couple the first gate of the first FET to the first routing track can be formed. A second conductive trace configured to conductively couple the second gate of the second FET to the second routing track can be formed.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: September 13, 2022
    Assignee: Tokyo Electron Limited
    Inventors: Jeffrey Smith, Anton J. deVilliers, Kandabara N. Tapily, Subhadeep Kal, Gerrit J. Leusink
  • Patent number: 11443953
    Abstract: A processing method includes receiving a substrate containing a base layer having a mandrel pattern formed thereon containing a number of features, conformally depositing a silicon oxide film over the mandrel pattern by coating surfaces of the substrate with a metal-containing catalyst layer, and in the absence of any oxidizing and hydrolyzing agent, exposing the substrate to a process gas containing a silanol gas at a substrate temperature selected to yield a preferred level of stress in the silicon oxide film. The method further includes removing the silicon oxide film from upper surfaces of the mandrel pattern and lower surfaces adjacent the mandrel pattern to leave behind silicon oxide sidewall spacers on sidewalls of the mandrel pattern, and removing the mandrel pattern from the substrate to leave behind the silicon oxide sidewall spacers that form a new pattern having double the number of features of the removed mandrel pattern.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: September 13, 2022
    Assignee: Tokyo Electron Limited
    Inventors: Kandabara N. Tapily, Anton deVilliers, Gerrit J. Leusink
  • Publication number: 20220139776
    Abstract: A method for filling recessed features with a low-resistivity metal includes providing a patterned substrate containing a recessed feature formed in a first layer and a second layer that is exposed in the recessed feature, pre-treating the substrate with a surface modifier that increases metal deposition selectivity on the second layer relative to on the first layer, and depositing a metal layer on the substrate by vapor phase deposition, where the metal layer is preferentially deposited on the second layer in the recessed feature. The method further includes removing metal nuclei deposited on the first layer, including on a field area and on sidewalls of the first layer in the recessed feature, to selectively form the metal layer on the second layer in the recessed feature, where the removing includes exposing the patterned substrate to an etching gas containing ozone.
    Type: Application
    Filed: October 21, 2021
    Publication date: May 5, 2022
    Inventors: Kai-Hung Yu, David L. O'Meara, Hisashi Higuchi, Hirokazu Aizawa, Omid Zandi, Cory Wajda, Gerrit J. Leusink
  • Publication number: 20210313189
    Abstract: A system for processing semiconductor wafers, the system including: a processing chamber; a heat source; a substrate holder configured to expose a semiconductor wafer to the heat source; a first electrode configured to be detachably coupled to a first major surface of a semiconductor wafer; and a second electrode coupled to the substrate holder, the first electrode and the second electrode together configured to apply an electric field in the semiconductor wafer.
    Type: Application
    Filed: February 25, 2021
    Publication date: October 7, 2021
    Inventors: David Hurley, Ioan Domsa, Ian Colgan, Gerhardus Van Der Linde, Patrick Hughes, Maciej Burel, Barry Clarke, Mihaela Ioana Popovici, Lars-Ake Ragnarsson, Gerrit J. Leusink, Robert Clark, Dina Triyoso
  • Patent number: 10923392
    Abstract: A semiconductor device is provided. The semiconductor device can have a substrate including dielectric material. A plurality of narrow interconnect openings can be formed within said dielectric material. In addition, a plurality of wide interconnect openings can be formed within said dielectric material. The semiconductor device can include a first metal filling the narrow interconnect openings to form an interconnect structure and conformally covering a surface of the wide interconnect openings formed in the dielectric material, and a second metal formed over the first metal and encapsulated by the first metal to form another interconnect structure within the wide interconnect openings.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: February 16, 2021
    Assignee: Tokyo Electron Limited
    Inventors: Soo Doo Chae, Jeffrey Smith, Gerrit J. Leusink, Robert D. Clark, Kai-Hung Yu
  • Publication number: 20210028169
    Abstract: Aspects of the disclosure provide a method for forming a semiconductor apparatus. The method includes forming a first field-effect transistor (FET) that includes a first gate on a substrate of the semiconductor apparatus. The method includes forming a second FET that is stacked on the first FET along a direction substantially perpendicular to the substrate and includes a second gate. The method includes forming a first routing track and a second routing track that is electrically isolated from the first routing track. Each of the first and second routing tracks is provided on a routing plane stacked on the second FET along the direction. A first conductive trace configured to conductively couple the first gate of the first FET to the first routing track can be formed. A second conductive trace configured to conductively couple the second gate of the second FET to the second routing track can be formed.
    Type: Application
    Filed: September 30, 2020
    Publication date: January 28, 2021
    Applicant: Tokyo Electron Limited
    Inventors: Jeffrey Smith, Anton J. deVilliers, Kandabara N. TAPILY, Subhadeep KAL, Gerrit J. LEUSINK
  • Patent number: 10833078
    Abstract: Aspects of the disclosure provide a semiconductor apparatus that comprises a first field-effect transistor (FET) formed on a substrate and comprising a first gate, a second FET stacked on the first FET along a direction substantially perpendicular to the substrate and comprising a second gate. The semiconductor apparatus also comprises a first routing track and a second routing track electrically isolated from the first routing track. Each of the first and second routing tracks is provided on a routing plane stacked on the second FET along said direction. The semiconductor apparatus also comprises a first conductive trace configured to conductively couple the first gate of the first FET to the first routing track, and a second conductive trace configured to conductively couple the second gate of the second FET to the second routing track.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: November 10, 2020
    Assignee: Tokyo Electron Limited
    Inventors: Jeffrey Smith, Anton J. deVilliers, Kandabara N. Tapily, Subhadeep Kal, Gerrit J. Leusink
  • Patent number: 10700009
    Abstract: A method is provided for void-free Ru metal filling of features in a substrate. The method includes providing a substrate containing features, depositing a Ru metal layer in the features, removing the Ru metal layer from a field area around an opening of the features, and depositing additional Ru metal in the features, where the additional Ru metal is deposited in the features at a higher rate than on the field area. According to one embodiment, the additional Ru metal is deposited until the features are fully filled with Ru metal.
    Type: Grant
    Filed: October 1, 2018
    Date of Patent: June 30, 2020
    Assignee: Tokyo Electron Limited
    Inventors: Kai-Hung Yu, Nicholas Joy, Eric Chih Fang Liu, David L. O'Meara, David Rosenthal, Masanobu Igeta, Cory Wajda, Gerrit J. Leusink
  • Publication number: 20200152473
    Abstract: A processing method includes receiving a substrate containing a base layer having a mandrel pattern formed thereon containing a number of features, conformally depositing a silicon oxide film over the mandrel pattern by coating surfaces of the substrate with a metal-containing catalyst layer, and in the absence of any oxidizing and hydrolyzing agent, exposing the substrate to a process gas containing a silanol gas at a substrate temperature selected to yield a preferred level of stress in the silicon oxide film. The method further includes removing the silicon oxide film from upper surfaces of the mandrel pattern and lower surfaces adjacent the mandrel pattern to leave behind silicon oxide sidewall spacers on sidewalls of the mandrel pattern, and removing the mandrel pattern from the substrate to leave behind the silicon oxide sidewall spacers that form a new pattern having double the number of features of the removed mandrel pattern.
    Type: Application
    Filed: November 13, 2019
    Publication date: May 14, 2020
    Inventors: Kandabara N. Tapily, Anton deVilliers, Gerrit J. Leusink
  • Patent number: 10580691
    Abstract: A substrate processing method is provided for metal filling of recessed features in a substrate. According to one embodiment, the method includes providing a substrate containing horizontally spaced nested and isolated recessed features, filling the nested and isolated recessed features with a blocking material, and performing in any order: a) sequentially first, removing the blocking material from the nested recessed features, and second, filling the nested recessed features with a first metal, and b) sequentially first, removing the blocking material from the isolated recessed features, and second, filling the isolated recessed features with a second metal that is different from the first metal. According to one embodiment, the first metal may include Ru metal and the second metal may include Cu metal. According to one embodiment, a microelectronic device containing metal filled recessed features is provided.
    Type: Grant
    Filed: June 6, 2018
    Date of Patent: March 3, 2020
    Assignee: Tokyo Electron Limited
    Inventors: Soo Doo Chae, Kaoru Maekawa, Jeffrey Smith, Nicholas Joy, Gerrit J. Leusink, Kai-Hung Yu
  • Patent number: 10541174
    Abstract: A semiconductor device is provided. The semiconductor device can have a substrate including dielectric material. A plurality of narrow interconnect openings can be formed within said dielectric material. In addition, a plurality of wide interconnect openings can be formed within said dielectric material. The semiconductor device can include a first metal filling the narrow interconnect openings to form an interconnect structure and conformally covering a surface of the wide interconnect openings formed in the dielectric material, and a second metal formed over the first metal and encapsulated by the first metal to form another interconnect structure within the wide interconnect openings.
    Type: Grant
    Filed: January 19, 2018
    Date of Patent: January 21, 2020
    Assignee: Tokyo Electron Limited
    Inventors: Soo Doo Chae, Jeffrey Smith, Gerrit J. Leusink, Robert D. Clark, Kai-Hung Yu
  • Publication number: 20200006129
    Abstract: A semiconductor device is provided. The semiconductor device can have a substrate including dielectric material. A plurality of narrow interconnect openings can be formed within said dielectric material. In addition, a plurality of wide interconnect openings can be formed within said dielectric material. The semiconductor device can include a first metal filling the narrow interconnect openings to form an interconnect structure and conformally covering a surface of the wide interconnect openings formed in the dielectric material, and a second metal formed over the first metal and encapsulated by the first metal to form another interconnect structure within the wide interconnect openings.
    Type: Application
    Filed: September 5, 2019
    Publication date: January 2, 2020
    Applicant: Tokyo Electron Limited
    Inventors: Soo Doo CHAE, Jeffrey SMITH, Gerrit J. LEUSINK, Robert D. CLARK, Kai-Hung YU
  • Patent number: 10453681
    Abstract: Embodiments of the invention describe methods for selective vertical growth of dielectric material on a dielectric substrate. According to one embodiment, the method includes providing a planarized substrate containing a first material having a recessed feature that is filled with a second material, selectively depositing a graphene layer on the second material relative to the first material, selectively depositing a SiO2 film on the first material relative to the graphene layer, and removing the graphene layer from the substrate. According to one embodiment, the first material includes a dielectric material and the second material includes a metal layer.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: October 22, 2019
    Assignee: Tokyo Electron Limited
    Inventors: Kandabara N. Tapily, Takashi Matsumoto, Yusaku Kashiwagi, Gerrit J. Leusink
  • Patent number: 10426001
    Abstract: A processing system is disclosed, having a process chamber that houses a substrate for exposure of a surface of the substrate to a travelling electromagnetic (EM) wave. The processing system also includes an EM wave transmission antenna configured to launch the travelling EM wave into the process chamber for the travelling EM wave to propagate in a direction substantially parallel to the surface of the substrate. The processing system also includes a power coupling system configured to supply EM energy into the EM wave transmission antenna to generate the travelling EM wave at a prescribed output power and in a prescribed EM wave mode during treatment of the substrate. The processing system also includes an EM wave receiving antenna configured to absorb the travelling EM wave after propagation through the process chamber.
    Type: Grant
    Filed: March 3, 2014
    Date of Patent: September 24, 2019
    Assignee: Tokyo Electron Limited
    Inventors: Ronald Nasman, Mirko Vukovic, Gerrit J. Leusink, Rodney L. Robison, Robert D. Clark
  • Patent number: 10410861
    Abstract: Methods for void-free material filling of fine recessed features have been disclosed in various embodiments. According to one embodiment, the method includes a) providing a substrate containing a recessed feature having an opening, a sidewall and a bottom, the sidewall including an area of retrograde profile relative to a direction extending from a top of the recessed feature to the bottom of the recessed feature, b) depositing an amount of a material in the recessed feature, the material having a greater thickness at the bottom than on the sidewall of the recessed feature, c) stopping the depositing in step b) before the recessed feature is fully filled with the material, d) etching a portion of the material from the recessed feature, and e) depositing an additional amount of the material to fully fill the recessed feature with the material without any voids in the recessed feature.
    Type: Grant
    Filed: March 7, 2018
    Date of Patent: September 10, 2019
    Assignee: Tokyo Electron Limited
    Inventors: Kandabara N. Tapily, Gerrit J. Leusink
  • Patent number: 10378105
    Abstract: Embodiments of the invention provide methods for selective deposition on different materials using a surface treatment. According to one embodiment, the method includes providing a substrate containing a first material layer having a first surface and a second material layer having a second surface, and performing a chemical oxide removal process that terminates that second surface with hydroxyl groups. The method further includes modifying the second surface by exposure to a process gas containing a hydrophobic functional group, the modifying substituting the hydroxyl groups on the second surface with the hydrophobic functional group, and selectively depositing a metal-containing layer on the first surface but not on the modified second surface by exposing the substrate to a deposition gas.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: August 13, 2019
    Assignee: Tokyo Electron Limited
    Inventors: Kai-Hung Yu, Kandabara N. Tapily, Takahiro Hakamata, Subhadeep Kal, Gerrit J. Leusink
  • Publication number: 20190172828
    Abstract: Aspects of the disclosure provide a semiconductor apparatus that comprises a first field-effect transistor (FET) formed on a substrate and comprising a first gate, a second FET stacked on the first FET along a direction substantially perpendicular to the substrate and comprising a second gate. The semiconductor apparatus also comprises a first routing track and a second routing track electrically isolated from the first routing track. Each of the first and second routing tracks is provided on a routing plane stacked on the second FET along said direction. The semiconductor apparatus also comprises a first conductive trace configured to conductively couple the first gate of the first FET to the first routing track, and a second conductive trace configured to conductively couple the second gate of the second FET to the second routing track.
    Type: Application
    Filed: November 30, 2018
    Publication date: June 6, 2019
    Applicant: Tokyo Electron Limited
    Inventors: Jeffrey SMITH, Anton J. deVilliers, Kandabara N. Tapily, Subhadeep Kal, Gerrit J. Leusink