Abstract: A method is provided for at least partially filling a feature in a substrate. The method includes providing a substrate containing a feature, depositing a ruthenium (Ru) metal layer to at least partially fill the feature, and heat-treating the substrate to reflow the Ru metal layer in the feature.

Abstract: Techniques herein include systems and methods that provide a spatially-controlled or pixel-based projection of light onto a substrate to tune various substrate properties. A given pixel-based image projected on to a substrate surface can be based on a substrate signature. The substrate signature can spatially represent non-uniformities across the surface of the substrate. Such non-uniformities can include energy, heat, critical dimensions, photolithographic exposure dosages, etc. Such pixel-based light projection can be used to tune various properties of substrates, including tuning of critical dimensions, heating uniformity, evaporative cooling, and generation of photo-sensitive agents. Combining such pixel-based light projection with photolithographic patterning processes and/or heating processes improves processing uniformity and decreases defectivity. Embodiments can include using a digital light processing (DLP) chip, grating light valve (GLV), or other grid-based micro projection technology.

Abstract: Embodiments of the invention describe a method of corner rounding and trimming of nanowires used in semiconductor devices. According to one embodiment, the method includes providing in a process chamber a plurality of nanowires separated from each other by a void, where the plurality of nanowires have a height and at least substantially right angle corners, forming an oxidized surface layer on the plurality of nanowires using an oxidizing microwave plasma, removing the oxidized surface layer to trim the height and round the corners of the plurality of nanowires, and repeating the forming and removing at least once until the plurality of nanowires have a desired trimmed height and rounded corners.

Abstract: A method for selective bottom-up filling of recessed features with a low resistivity metal for semiconductor devices is described in several embodiments. The method includes providing a substrate containing a patterned dielectric layer having a recessed feature with dielectric layer surfaces and a metal-containing surface on a bottom of the recessed feature, reacting the dielectric layer surfaces with a reactant gas containing a hydrophobic functional group to form hydrophobic dielectric layer surfaces, and at least substantially filling the recessed feature with a metal in a bottom-up gas phase deposition process that hinders deposition of the metal on the hydrophobic dielectric layer surfaces. According to one embodiment, the metal is selected from the group consisting of ruthenium (Ru), cobalt (Co), aluminum (Al), iridium (Ir), iridium (Ir), rhodium (Rh), osmium (Os), palladium (Pd), platinum (Pt), nickel (Ni), and a combination thereof.

Abstract: A germanium-containing semiconductor device and a method for forming a germanium-containing semiconductor device are described. The method includes providing a germanium-containing substrate, depositing an aluminum-containing diffusion barrier layer on the germanium-containing substrate, depositing a high-k layer on the aluminum-containing diffusion barrier layer, and exposing the high-k layer to atomic oxygen to reduce the equivalent oxide thickness (EOT) of the high-k layer while avoiding oxidizing the germanium-containing substrate. The germanium-containing semiconductor device includes a germanium-containing substrate, an aluminum-containing diffusion barrier layer on the germanium-containing substrate, and a high-k layer on the aluminum-containing diffusion barrier layer, where the high-k layer has been exposed to atomic oxygen to reduce the EOT of the high-k layer while avoiding oxidizing the germanium-containing substrate.

Abstract: A method is provided for at least partially filling a feature in a substrate. The method includes providing a substrate containing a feature, depositing a ruthenium (Ru) metal layer to at least partially fill the feature, and heat-treating the substrate to reflow the Ru metal layer in the feature.

Abstract: Embodiments of the invention describe methods for forming a semiconductor device. According to one embodiment, the method includes depositing an aluminum-doped high-k film on a substrate by atomic layer deposition (ALD) that includes: a) pulsing a metal-containing precursor gas into a process chamber containing the substrate, b) pulsing an aluminum-containing precursor gas into the process chamber, where a) and b) are sequentially performed without an intervening oxidation step, and c) pulsing an oxygen-containing gas into the process chamber. The method can further include heat-treating the aluminum-doped high-k film to crystallize or increase the crystallization of the film.

Abstract: Techniques herein include systems and methods that provide a spatially-controlled or pixel-based projection of light onto a substrate to tune various substrate properties. A given pixel-based image projected on to a substrate surface can be based on a substrate signature. The substrate signature can spatially represent non-uniformities across the surface of the substrate. Such non-uniformities can include energy, heat, critical dimensions, photolithographic exposure dosages, etc. Such pixel-based light projection can be used to tune various properties of substrates, including tuning of critical dimensions, heating uniformity, evaporative cooling, and generation of photo-sensitive agents. Combining such pixel-based light projection with photolithographic patterning processes and/or heating processes improves processing uniformity and decreases defectivity. Embodiments can include using a digital light processing (DLP) chip, grating light valve (GLV), or other grid-based micro projection technology.

Abstract: Techniques herein include systems and methods that provide a spatially-controlled or pixel-based projection of light onto a substrate to tune various substrate properties. A given pixel-based image projected on to a substrate surface can be based on a substrate signature. The substrate signature can spatially represent non-uniformities across the surface of the substrate. Such non-uniformities can include energy, heat, critical dimensions, photolithographic exposure dosages, etc. Such pixel-based light projection can be used to tune various properties of substrates, including tuning of critical dimensions, heating uniformity, evaporative cooling, and generation of photo-sensitive agents. Combining such pixel-based light projection with photolithographic patterning processes and/or heating processes improves processing uniformity and decreases defectivity. Embodiments can include using a digital light processing (DLP) chip, grating light valve (GLV), or other grid-based micro projection technology.

Abstract: A processing system is disclosed, having a process chamber that houses a substrate for exposure of a surface of the substrate to a travelling electromagnetic (EM) wave. The processing system also includes an EM wave transmission antenna configured to launch the travelling EM wave into the process chamber for the travelling EM wave to propagate in a direction substantially parallel to the surface of the substrate. The processing system also includes a power coupling system configured to supply EM energy into the EM wave transmission antenna to generate the travelling EM wave at a prescribed output power and in a prescribed EM wave mode during treatment of the substrate. The processing system also includes an EM wave receiving antenna configured to absorb the travelling EM wave after propagation through the process chamber.

Abstract: A method is provided for forming a metal silicide layer on a substrate. According to one embodiment the method includes providing the substrate in a process chamber, exposing the substrate at a first substrate temperature to a plasma generated from a deposition gas containing a metal precursor, where the plasma exposure forms a conformal metal-containing layer on the substrate in a self-limiting process. The method further includes exposing the metal-containing layer at a second substrate temperature to a reducing gas in the absence of a plasma, where the exposing steps are alternatively performed at least once to form the metal silicide layer, and the deposition gas does not contain the reducing gas. The method provides conformal metal silicide formation in deep trenches with high aspect ratios.

Abstract: A gas diffuser assembly and vapor deposition system for use therein are described. The gas diffuser assembly includes a gas diffuser manifold configured to be coupled to a substrate processing system and arranged to introduce a process gas from a gas outlet into the substrate processing system in a direction substantially normal to a surface of a substrate to create a stagnation flow pattern over the surface. The gas diffuser manifold includes a gas inlet, a stagnation plate, and a diffusion member.

Abstract: A method is provided for forming a metal silicide layer on a substrate. According to one embodiment the method includes providing the substrate in a process chamber, exposing the substrate at a first substrate temperature to a plasma generated from a deposition gas containing a metal precursor, where the plasma exposure forms a conformal metal-containing layer on the substrate in a self-limiting process. The method further includes exposing the metal-containing layer at a second substrate temperature to a reducing gas in the absence of a plasma, where the exposing steps are alternatively performed at least once to form the metal silicide layer, and the deposition gas does not contain the reducing gas. The method provides conformal metal silicide formation in deep trenches with high aspect ratios.

Abstract: A method is provided for forming a semiconductor device containing a buried threshold voltage adjustment layer. The method includes providing a substrate containing an interface layer, depositing a first high-k film on the interface layer, depositing a threshold voltage adjustment layer on the first high-k film, and depositing a second high-k film on the threshold voltage adjustment layer such that the threshold voltage adjustment layer is interposed between the first and second high-k films. The semiconductor device containing a patterned gate stack is described.

Abstract: A gas diffuser assembly and vapor deposition system for use therein are described. The gas diffuser assembly includes a gas diffuser manifold configured to be coupled to a substrate processing system and arranged to introduce a process gas from a gas outlet into the substrate processing system in a direction substantially normal to a surface of a substrate to create a stagnation flow pattern over the surface. The gas diffuser manifold includes a gas inlet, a stagnation plate, and a diffusion member.

Abstract: A method and system for depositing a layer from a vaporized solid precursor. The method includes providing a substrate in a process chamber of a deposition system, forming a precursor vapor by light-induced vaporization of a solid precursor, and exposing the substrate to a process gas containing the precursor vapor to deposit a layer including at least one element from the precursor vapor on the substrate.

Abstract: A method for forming an aluminum-doped metal (tantalum or titanium) carbonitride gate electrode for a semiconductor device is described. The method includes providing a substrate containing a dielectric layer thereon, and forming the gate electrode on the dielectric layer in the absence of plasma. The gate electrode is formed by depositing a metal carbonitride film, and adsorbing an atomic layer of an aluminum precursor on the metal carbonitride film. The steps of depositing and adsorbing may be repeated a desired number of times until the aluminum-doped metal carbonitride gate electrode has a desired thickness.

Abstract: A method is provided for forming a semiconductor device containing a buried threshold voltage adjustment layer. The method includes providing a substrate containing an interface layer, depositing a first high-k film on the interface layer, depositing a threshold voltage adjustment layer on the first high-k film, and depositing a second high-k film on the threshold voltage adjustment layer such that the threshold voltage adjustment layer is interposed between the first and second high-k films. The semiconductor device containing a patterned gate stack is described.

Abstract: A method is provided for forming a semiconductor device containing a buried threshold voltage adjustment layer. The method includes providing a substrate containing an interface layer, depositing a first high-k film on the interface layer, depositing a threshold voltage adjustment layer on the first high-k film, and depositing a second high-k film on the threshold voltage adjustment layer such that the threshold voltage adjustment layer is interposed between the first and second high-k films. The semiconductor device containing a patterned gate stack is described.

Abstract: A high conductance, multi-tray film precursor evaporation system coupled with a high conductance vapor delivery system is described for increasing the deposition rate by increasing exposed surface area of film precursor. The multi-tray film precursor evaporation system includes one or more trays. Each tray is configured to support and retain film precursor in, for example, solid powder form or solid tablet form. Additionally, each tray is configured to provide for a high conductance flow of carrier gas over the film precursor while the film precursor is heated. For example, the carrier gas flows inward over the film precursor, and vertically upward through a flow channel within the stackable trays and through an outlet in the solid precursor evaporation system.