Abstract: A method is provided for void-free Ru metal filling of features in a substrate. The method includes providing a substrate containing features, depositing a Ru metal layer in the features, removing the Ru metal layer from a field area around an opening of the features, and depositing additional Ru metal in the features, where the additional Ru metal is deposited in the features at a higher rate than on the field area. According to one embodiment, the additional Ru metal is deposited until the features are fully filled with Ru metal.

Abstract: Embodiments of the invention provide a wrap-around contact integration scheme that includes sidewall protection during contact formation. According to one embodiment, a substrate processing method includes providing a substrate containing raised contacts in a first dielectric film and a second dielectric film above the first dielectric film, depositing a metal-containing film on the second dielectric film, and forming a patterned metal-containing film by etching mask openings in the metal-containing film. The method further includes anisotropically etching recessed features in the second dielectric film above the raised contacts using the patterned metal-containing film as a mask, where the anisotropically etching forms a metal-containing sidewall protection film by redeposition of a portion of the patterned metal-containing film on sidewalls of the recessed features.

Abstract: Techniques herein include a process chamber for depositing thin films to backside surfaces of wafers to reduce wafer bowing and distortion. A substrate support provides an annular perimeter seal around the bottom and/or side of the wafer which allows the majority of the substrate backside to be exposed to a process environment. A supported wafer separates the chamber into lower and upper chambers that provide different process environments. The lower section of the processing chamber includes deposition hardware configured to apply and remove thin films. The upper section can remain a chemically inert environment, protecting the existing features on the top surface of the wafer. Multiple exhausts and differential pressures are used to prevent deposition gasses from accessing the working surface of a wafer.

Abstract: Methods for integration of conformal barrier layers and Ru metal liners with Cu metallization in semiconductor manufacturing are described in several embodiments. According to one embodiment, the method includes providing a substrate containing a recessed feature, depositing a barrier layer in the recessed feature, depositing a Ru metal liner on the barrier layer, and exposing the substrate to an oxidation source gas to oxidize the barrier layer through the Ru metal liner. The method further includes filling the recessed feature with CuMn metal using an ionized physical vapor deposition (IPVD) process, heat-treating the substrate to diffuse Mn from the CuMn metal to the oxidized barrier layer, and reacting the diffused Mn with the oxidized barrier layer to form a Mn-containing diffusion barrier.

Abstract: A substrate processing method is provided for metal filling of recessed features in a substrate. According to one embodiment, the method includes providing a substrate containing horizontally spaced nested and isolated recessed features, filling the nested and isolated recessed features with a blocking material, and performing in any order: a) sequentially first, removing the blocking material from the nested recessed features, and second, filling the nested recessed features with a first metal, and b) sequentially first, removing the blocking material from the isolated recessed features, and second, filling the isolated recessed features with a second metal that is different from the first metal. According to one embodiment, the first metal may include Ru metal and the second metal may include Cu metal. According to one embodiment, a microelectronic device containing metal filled recessed features is provided.

Abstract: Embodiments of the invention describe methods for selective vertical growth of dielectric material on a dielectric substrate. According to one embodiment, the method includes providing a planarized substrate containing a first material having a recessed feature that is filled with a second material, selectively depositing a graphene layer on the second material relative to the first material, selectively depositing a SiO2 film on the first material relative to the graphene layer, and removing the graphene layer from the substrate. According to one embodiment, the first material includes a dielectric material and the second material includes a metal layer.

Abstract: Methods for void-free material filling of fine recessed features have been disclosed in various embodiments. According to one embodiment, the method includes a) providing a substrate containing a recessed feature having an opening, a sidewall and a bottom, the sidewall including an area of retrograde profile relative to a direction extending from a top of the recessed feature to the bottom of the recessed feature, b) depositing an amount of a material in the recessed feature, the material having a greater thickness at the bottom than on the sidewall of the recessed feature, c) stopping the depositing in step b) before the recessed feature is fully filled with the material, d) etching a portion of the material from the recessed feature, and e) depositing an additional amount of the material to fully fill the recessed feature with the material without any voids in the recessed feature.

Abstract: Embodiments of the invention provide methods for selective film deposition using a surface pretreatment. According to one embodiment, the method includes providing a substrate containing a dielectric layer and a metal layer, exposing the substrate to a reactant gas containing a molecule that forms self-assembled monolayers (SAMs) on the substrate, and thereafter, selectively depositing a metal oxide film on a surface of the dielectric layer relative to a surface of the metal layer by exposing the substrate to a deposition gas.

Abstract: A method is provided for at least partially filling a feature in a substrate. The method includes providing a substrate containing a feature, depositing a ruthenium (Ru) metal layer to at least partially fill the feature, and heat-treating the substrate to reflow the Ru metal layer in the feature.

Abstract: A semiconductor device is provided. The semiconductor device can have a substrate including dielectric material. A plurality of narrow interconnect openings can be formed within said dielectric material. In addition, a plurality of wide interconnect openings can be formed within said dielectric material. The semiconductor device can include a first metal filling the narrow interconnect openings to form an interconnect structure and conformally covering a surface of the wide interconnect openings formed in the dielectric material, and a second metal formed over the first metal and encapsulated by the first metal to form another interconnect structure within the wide interconnect openings.

Abstract: A method for selective bottom-up filling of recessed features with a low resistivity metal for semiconductor devices is described in several embodiments. The method includes providing a substrate containing a patterned dielectric layer having a recessed feature with dielectric layer surfaces and a metal-containing surface on a bottom of the recessed feature, reacting the dielectric layer surfaces with a reactant gas containing a hydrophobic functional group to form hydrophobic dielectric layer surfaces, and at least substantially filling the recessed feature with a metal in a bottom-up gas phase deposition process that hinders deposition of the metal on the hydrophobic dielectric layer surfaces. According to one embodiment, the metal is selected from the group consisting of ruthenium (Ru), cobalt (Co), aluminum (Al), iridium (Ir), iridium (Ir), rhodium (Rh), osmium (Os), palladium (Pd), platinum (Pt), nickel (Ni), and a combination thereof.

Abstract: Embodiments of the invention describe a method of corner rounding and trimming of nanowires used in semiconductor devices. According to one embodiment, the method includes providing in a process chamber a plurality of nanowires separated from each other by a void, where the plurality of nanowires have a height and at least substantially right angle corners, forming an oxidized surface layer on the plurality of nanowires using an oxidizing microwave plasma, removing the oxidized surface layer to trim the height and round the corners of the plurality of nanowires, and repeating the forming and removing at least once until the plurality of nanowires have a desired trimmed height and rounded corners.

Abstract: Embodiments of the invention provide methods for selective film deposition using a surface pretreatment. According to one embodiment, the method includes providing a substrate containing a dielectric layer and a metal layer, exposing the substrate to a reactant gas containing a molecule that forms self-assembled monolayers (SAMs) on the substrate, and thereafter, selectively depositing a metal oxide film on a surface of the dielectric layer relative to a surface of the metal layer by exposing the substrate to a deposition gas.

Abstract: Embodiments of the invention provide a wrap-around contact integration scheme that includes sidewall protection during contact formation. According to one embodiment, a substrate processing method includes providing a substrate containing raised contacts in a first dielectric film and a second dielectric film above the first dielectric film, depositing a metal-containing film on the second dielectric film, and forming a patterned metal-containing film by etching mask openings in the metal-containing film. The method further includes anisotropically etching recessed features in the second dielectric film above the raised contacts using the patterned metal-containing film as a mask, where the anisotropically etching forms a metal-containing sidewall protection film by redeposition of a portion of the patterned metal-containing film on sidewalls of the recessed features.

Abstract: A method of void-less metal filling of recessed features in a substrate is provided. The method includes providing a substrate containing recessed features therein, and filling the recessed features with a metal, where the metal is deposited in the recessed features by gas phase deposition at substrate temperature and a gas pressure that promotes bottom-up void-less filling. According to one embodiment, the metal is selected from the group consisting of Ru, Rh, Os, Pd, Ir, Pt, Ni, Co, W, and a combination thereof.

Abstract: Embodiments of the invention provide methods for selective deposition on different materials using a surface treatment. According to one embodiment, the method includes providing a substrate containing a first material layer having a first surface and a second material layer having a second surface, and performing a chemical oxide removal process that terminates that second surface with hydroxyl groups. The method further includes modifying the second surface by exposure to a process gas containing a hydrophobic functional group, the modifying substituting the hydroxyl groups on the second surface with the hydrophobic functional group, and selectively depositing a metal-containing layer on the first surface but not on the modified second surface by exposing the substrate to a deposition gas.

Abstract: A method is provided for at least partially filling a feature in a substrate. The method includes providing a substrate containing a feature, depositing a ruthenium (Ru) metal layer to at least partially fill the feature, and heat-treating the substrate to reflow the Ru metal layer in the feature.

Abstract: A method for material deposition is described in several embodiments. According to one embodiment, the method includes providing a substrate defining features to receive a deposition of material, initiating a flow of a Ru carbonyl precursor to the substrate, the Ru carbonyl precursor decomposing within the defined features such that a Ru metal film is deposited on surfaces of the defined features and CO gas is released, and stopping the flow of the Ru carbonyl precursor to the substrate. The method further includes flowing additional CO gas to the substrate after stopping the flow of the Ru carbonyl precursor to the substrate, and repeatedly cycling between process steps of flowing the Ru carbonyl precursor to the substrate and flowing the additional CO gas to the substrate. In one embodiment, the Ru carbonyl precursor contains Ru3(CO)12.

Abstract: Methods for integration of conformal barrier layers and Ru metal liners with Cu metallization in semiconductor manufacturing are described in several embodiments. According to one embodiment, the method includes providing a substrate containing a recessed feature, depositing a barrier layer in the recessed feature, depositing a Ru metal liner on the barrier layer, and exposing the substrate to an oxidation source gas to oxidize the barrier layer through the Ru metal liner. The method further includes filling the recessed feature with CuMn metal using an ionized physical vapor deposition (IPVD) process, heat-treating the substrate to diffuse Mn from the CuMn metal to the oxidized barrier layer, and reacting the diffused Mn with the oxidized barrier layer to form a Mn-containing diffusion barrier.

Abstract: Techniques herein include systems and methods that provide a spatially-controlled or pixel-based projection of light onto a substrate to tune various substrate properties. A given pixel-based image projected on to a substrate surface can be based on a substrate signature. The substrate signature can spatially represent non-uniformities across the surface of the substrate. Such non-uniformities can include energy, heat, critical dimensions, photolithographic exposure dosages, etc. Such pixel-based light projection can be used to tune various properties of substrates, including tuning of critical dimensions, heating uniformity, evaporative cooling, and generation of photo-sensitive agents. Combining such pixel-based light projection with photolithographic patterning processes and/or heating processes improves processing uniformity and decreases defectivity. Embodiments can include using a digital light processing (DLP) chip, grating light valve (GLV), or other grid-based micro projection technology.