Patents by Inventor Ghavam G. Shahidi

Ghavam G. Shahidi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190371246
    Abstract: A pixel circuit includes a first transistor, a second transistor connected to a first source/drain of the first transistor, a circuit element connected to a gate of the first transistor and ground and configured to receive a select input and maintain the select input less than or equal to a potential of the ground, and a resistive element connected to an organic light emitting diode (OLED) and a first source/drain of the second transistor.
    Type: Application
    Filed: August 15, 2019
    Publication date: December 5, 2019
    Inventors: Bahman Hekmatshoartabari, Ghavam G. Shahidi
  • Patent number: 10475871
    Abstract: An apparatus includes a junction field-effect transistor (JFET) and a set of one or more serially-connected diodes. The JFET includes a first layer including silicon of a first conductivity type, a gate, and first and second terminals. The gate includes a second layer formed on the first layer and including intrinsic amorphous hydrogenated silicon, a third layer formed on the second layer and including amorphous hydrogenated silicon of a second conductivity type, and a conductive layer formed on the third layer. Each of the first and second terminals includes a fourth layer formed on the first layer, the fourth layer including crystalline hydrogenated silicon of the first conductivity type, and a conductive layer formed on the fourth layer. Each of the serially-connected diodes has first and second terminals, a first of the serially-connected diodes having the first terminal connected to the second terminal of the JFET.
    Type: Grant
    Filed: November 8, 2016
    Date of Patent: November 12, 2019
    Assignee: International Business Machines Corporation
    Inventors: Bahman Hekmatshoartabari, Ghavam G. Shahidi
  • Publication number: 20190305067
    Abstract: An apparatus includes a junction field-effect transistor (JFET) and a set of one or more serially-connected diodes. The JFET includes a first layer including silicon of a first conductivity type, a gate, and first and second terminals. The gate includes a second layer formed on the first layer and including intrinsic amorphous hydrogenated silicon, a third layer formed on the second layer and including amorphous hydrogenated silicon of a second conductivity type, and a conductive layer formed on the third layer. Each of the first and second terminals includes a fourth layer formed on the first layer, the fourth layer including crystalline hydrogenated silicon of the first conductivity type, and a conductive layer formed on the fourth layer. Each of the serially-connected diodes has first and second terminals, a first of the serially-connected diodes having the first terminal connected to the second terminal of the JFET.
    Type: Application
    Filed: June 4, 2019
    Publication date: October 3, 2019
    Inventors: Bahman Hekmatshoartabari, Ghavam G. Shahidi
  • Publication number: 20190299702
    Abstract: The present invention provides a method and a structure of electrical component assembly on flexible materials. In an exemplary embodiment, the method and the structure include patterning metal on a tape, creating one or more holes in the tape, attaching one or more electronic devices to the tape in the one or more holes such that a profile of the tape and the one or more electronic devices is less than a threshold, electrically connecting the one or more electronic devices to the patterned metal, cutting the tape, resulting in one or more component portions of the tape and one or more excess portions of the tape, where the one or more component portions comprises at least one of the one or more electronic devices, attached to the patterned metal, and bonding the one or more component portions to a ribbon.
    Type: Application
    Filed: June 18, 2019
    Publication date: October 3, 2019
    Inventors: Frank R. Libsch, Ghavam G. Shahidi
  • Publication number: 20190305103
    Abstract: A method is presented for forming a semiconductor device. The method may include forming a first gate structure on a first portion of a semiconductor material located on a surface of an insulating substrate, the first gate structure including a first sacrificial layer and a second sacrificial layer and forming a second gate structure on a second portion of the semiconductor material located on the surface of the insulating substrate, the second gate structure including a third sacrificial layer. The method further includes etching the first and second dielectric sacrificial layers to create a first contact region within the first gate structure and etching the third dielectric sacrificial layer to create a second contact region within the second gate structure. The method further includes forming silicide in at least the first and second contact regions of the first and second gate structures, respectively.
    Type: Application
    Filed: June 18, 2019
    Publication date: October 3, 2019
    Inventors: Bahman Hekmatshoartabari, Ghavam G. Shahidi
  • Publication number: 20190296181
    Abstract: A semiconductor structure for optical power conversion and a method of forming the semiconductor structure are provided. In an aspect, the method may include removing a first portion of the semiconductor structure from a first region, wherein the semiconductor structure comprises a layered photovoltaic structure on a silicon-on-insulator structure. A second portion of the semiconductor structure may be removed from a second region, wherein the second region is located adjacent to the first region, and wherein an insulator layer of the silicon-on-insulator structure is exposed by the removed second portion. A passivation layer pattern may be formed over the semiconductor structure. Electrodes may be formed on portions of the surfaces of the semiconductor structure that are uncovered by the passivation layer.
    Type: Application
    Filed: March 26, 2018
    Publication date: September 26, 2019
    Inventors: Ning Li, Kevin Han, William T. Spratt, Stephen W. Bedell, Devendra Sadana, Ghavam G. Shahidi
  • Patent number: 10423805
    Abstract: A private key of a public-private key pair with a corresponding identity is written to an integrated circuit including a processor, a non-volatile memory, and a cryptographic engine coupled to the processor and the non-volatile memory. The private key is written to the non-volatile memory. The integrated circuit is implemented in complementary metal-oxide semiconductor 14 nm or smaller technology. The integrated circuit is permanently modified, subsequent to the writing, such that further writing to the non-volatile memory is disabled and such that the private key can be read only by the cryptographic engine and not off-chip. Corresponding integrated circuits and wafers are also disclosed.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: September 24, 2019
    Assignee: International Business Machines Corporation
    Inventors: Richard H. Boivie, Eduard A. Cartier, Daniel J. Friedman, Kohji Hosokawa, Charanjit Jutla, Wanki Kim, Chandrasekara Kothandaraman, Chung Lam, Frank R. Libsch, Seiji Munetoh, Ramachandran Muralidhar, Vijay Narayanan, Dirk Pfeiffer, Devendra K. Sadana, Ghavam G. Shahidi, Robert L. Wisnieff
  • Patent number: 10424605
    Abstract: A method is presented for forming a semiconductor device. The method may include forming a first gate structure on a first portion of a semiconductor material located on a surface of an insulating substrate, the first gate structure including a first sacrificial layer and a second sacrificial layer and forming a second gate structure on a second portion of the semiconductor material located on the surface of the insulating substrate, the second gate structure including a third sacrificial layer. The method further includes etching the first and second dielectric sacrificial layers to create a first contact region within the first gate structure and etching the third dielectric sacrificial layer to create a second contact region within the second gate structure. The method further includes forming silicide in at least the first and second contact regions of the first and second gate structures, respectively.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: September 24, 2019
    Assignee: International Business Machines Corporation
    Inventors: Bahman Hekmatshoartabari, Ghavam G. Shahidi
  • Publication number: 20190288050
    Abstract: An apparatus includes transistor and a set of one or more serially-connected diodes coupled to the transistor. The transistor includes a gate, and first and second terminals. A first diode in the set of serially-connected diodes has a first terminal connected to the second terminal of the transistor. At least one of the diodes includes a first layer including silicon having a first type of carrier as its majority carrier, a first terminal, and a second terminal. The first terminal includes a second layer formed on the first layer, a third layer comprising amorphous hydrogenated silicon having a second type of carrier as its majority carrier formed on the second layer, and a conductive layer formed on the third layer. The second terminal includes a fourth layer comprising crystalline hydrogenated silicon of the first carrier type formed on the first layer, and a conductive layer formed on the fourth layer.
    Type: Application
    Filed: June 5, 2019
    Publication date: September 19, 2019
    Inventors: Bahman Hekmatshoartabari, Ghavam G. Shahidi
  • Publication number: 20190280128
    Abstract: Embodiments of the invention are directed to a method of forming a semiconductor device. A non-limiting example of the method includes forming a semiconductor layer within or on a portion of a substrate, wherein the semiconductor layer includes a first type of semiconductor material. A gate stack is formed over a first exposed surface of the semiconductor layer. A first hydrogenated and doped semiconductor layer is formed over a second exposed surface of the semiconductor layer. A second hydrogenated and doped semiconductor layer is formed over a third exposed surface of the semiconductor layer, wherein a lateral dimension of the first hydrogenated and doped semiconductor layer terminates at a first sidewall of the gate stack, and wherein a lateral dimension of the second hydrogenated and doped semiconductor layer terminates at a second sidewall of the gate stack.
    Type: Application
    Filed: May 24, 2019
    Publication date: September 12, 2019
    Inventors: Bahman Hekmatshoartabari, Ghavam G. Shahidi
  • Publication number: 20190273165
    Abstract: Embodiments of the invention are directed to a method of forming a semiconductor device. A non-limiting example of the method includes forming a semiconductor layer within or on a portion of a substrate, wherein the semiconductor layer includes a first type of semiconductor material. A gate stack is formed over a first exposed surface of the semiconductor layer. A first hydrogenated and doped semiconductor layer is formed over a second exposed surface of the semiconductor layer. A second hydrogenated and doped semiconductor layer is formed over a third exposed surface of the semiconductor layer, wherein a lateral dimension of the first hydrogenated and doped semiconductor layer terminates at a first sidewall of the gate stack, and wherein a lateral dimension of the second hydrogenated and doped semiconductor layer terminates at a second sidewall of the gate stack.
    Type: Application
    Filed: March 1, 2018
    Publication date: September 5, 2019
    Inventors: Bahman Hekmatshoartabari, Ghavam G. Shahidi
  • Patent number: 10391805
    Abstract: The present invention provides a method and a structure of electrical component assembly on flexible materials. In an exemplary embodiment, the method and the structure include patterning metal on a tape, creating one or more holes in the tape, attaching one or more electronic devices to the tape in the one or more holes such that a profile of the tape and the one or more electronic devices is less than a threshold, electrically connecting the one or more electronic devices to the patterned metal, cutting the tape, resulting in one or more component portions of the tape and one or more excess portions of the tape, where the one or more component portions comprises at least one of the one or more electronic devices, attached to the patterned metal, and bonding the one or more component portions to a ribbon.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: August 27, 2019
    Assignee: International Business Machines Corporation
    Inventors: Frank R. Libsch, Ghavam G. Shahidi
  • Patent number: 10396061
    Abstract: Dust-sized and light transparent semiconductor chips are provided and are used in a transparent electronic system. The dust-sized and light transparent semiconductor chips are composed entirely of materials that are transparent to visible light. The dust-sized and light transparent semiconductor chips are used as a component of a transparent electronic system.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: August 27, 2019
    Assignee: International Business Machines Corporation
    Inventors: Ning Li, Devendra K. Sadana, Stephen W. Bedell, Ghavam G. Shahidi, Theodore van Kessel
  • Patent number: 10388814
    Abstract: Photovoltaic devices including direct gap III-V absorber materials and operatively associated back structures enhance efficiency by enabling photon recycling. The back structures of the photovoltaic devices include wide bandgap III-V layers, highly doped (In)GaAs layers, patterned oxide layers and metal reflectors that directly contact the highly doped (In)GaAs layers through vias formed in the back structures. Localized ohmic contacts are formed in the back structures of the devices.
    Type: Grant
    Filed: June 10, 2017
    Date of Patent: August 20, 2019
    Assignee: International Business Machines Corporation
    Inventors: Bahman Hekmatshoartabari, Ali Khakifirooz, Ghavam G. Shahidi, Davood Shahrjerdi
  • Publication number: 20190252573
    Abstract: A method of forming an electrical device that includes epitaxially growing a first conductivity type semiconductor material of a type III-V semiconductor on a semiconductor substrate. The first conductivity type semiconductor material continuously extending along an entirety of the semiconductor substrate in a plurality of triangular shaped islands; and conformally forming a layer of type III-V semiconductor material having a second conductivity type on the plurality of triangular shaped islands to provide a textured surface of a photovoltaic device. A light emitting diode is formed on the textured surface of the photovoltaic device.
    Type: Application
    Filed: April 23, 2019
    Publication date: August 15, 2019
    Inventors: Stephen W. Bedell, Ning Li, Devendra K. Sadana, Ghavam G. Shahidi
  • Publication number: 20190244815
    Abstract: A hard mask and a method of creating thereof are provided. A first layer is deposited that is configured to provide at least one of a chemical and a mechanical adhesion to a layer immediately below it. A second layer is deposited having an etch selectivity that is faster than the first layer. A third layer is deposited having an etch selectivity that is slower than the first and second layers. The third layer has a composite strength that is higher than the first and second layers. A photoresist layer is deposited on top of the third layer and chemically removed above an inner opening. The third layer and part of the second layer are anisotropically etched through the inner opening. The second layer and the first layer are isotropically etched to create overhang regions of the third layer.
    Type: Application
    Filed: February 8, 2018
    Publication date: August 8, 2019
    Inventors: Frank Robert Libsch, Ghavam G. Shahidi, Ko-Tao Lee, Stephen M. Rossnagel
  • Publication number: 20190245246
    Abstract: A solid state electrochemical battery fabrication device and a method of creating the solid state electrochemical battery are provided. There is a first chamber comprising a first magnetron and a second chamber comprising a second magnetron, coupled to the first chamber. There is a third chamber comprising a vapor source for a polymer deposition, coupled to the second chamber. A Knudsen cell is coupled to the third chamber and configured to deposit lithium on a battery being fabricated. A linear hollow shaft connects the first, second, and third chambers, and provides a hermetic seal. A first telescopic arm having a housing is coupled to a first end of the hollow shaft and configured to extend out of its housing from the first chamber to the second chamber.
    Type: Application
    Filed: February 8, 2018
    Publication date: August 8, 2019
    Inventors: Frank Robert Libsch, Ghavam G. Shahidi, Ko-Tao Lee, Stephen M. Rossnagel
  • Publication number: 20190245247
    Abstract: A solid state electrochemical battery and a method of creation thereof are provided. There is a first conductive electrode on top of a substrate. There is a first polar conductor layer on top of the conductive electrode layer. A first solid electrolyte layer is on top of the first polar conductor layer. There is a second polar conductor layer on top of the first solid electrolyte layer and a second conductive electrode layer on top of the second polar conductor layer. A third polar conductor layer is on top of the second conductive electrode layer and a second solid electrolyte layer is on top of the third polar conductor layer. There is a fourth polar conductor layer on top of the second solid electrolyte layer and a third conductive electrode layer on top of the fourth polar conductor layer.
    Type: Application
    Filed: February 8, 2018
    Publication date: August 8, 2019
    Inventors: Frank Robert Libsch, Ghavam G. Shahidi, Ko-Tao Lee, Stephen M. Rossnagel
  • Patent number: 10355164
    Abstract: A method of forming an electrical device that includes epitaxially growing a first conductivity type semiconductor material of a type III-V semiconductor on a semiconductor substrate. The first conductivity type semiconductor material continuously extending along an entirety of the semiconductor substrate in a plurality of triangular shaped islands; and conformally forming a layer of type III-V semiconductor material having a second conductivity type on the plurality of triangular shaped islands to provide a textured surface of a photovoltaic device. A light emitting diode is formed on the textured surface of the photovoltaic device.
    Type: Grant
    Filed: April 2, 2018
    Date of Patent: July 16, 2019
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Ning Li, Devendra K. Sadana, Ghavam G. Shahidi
  • Patent number: 10347599
    Abstract: A method of forming a semiconductor detector including: forming a p-n junction diode in an active device layer of a silicon-on-insulator (SOI) substrate, the active device layer being formed on an insulator layer of the SOI substrate; forming a first opening through the insulator layer to access a backside of a first doped region of the diode, the first doped region underlying a second doped region of the diode; forming a back contact on a back surface of the first doped region and electrically connecting with the first doped region; forming a conductive interconnect layer on an upper surface of the SOI substrate, the interconnect layer including a first top contact providing electrical connection with the second doped region; and forming an electrode in the first opening on the backside of the detector structure, the electrode providing electrical connection with the back contact of the diode.
    Type: Grant
    Filed: July 11, 2018
    Date of Patent: July 9, 2019
    Assignee: International Business Machines Corporation
    Inventors: Bahman Hekmatshoartabari, Ghavam G. Shahidi