Patents by Inventor Ghavam G. Shahidi

Ghavam G. Shahidi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11063161
    Abstract: A method of forming a photovoltaic device that includes epitaxially growing a first conductivity type semiconductor material of a type III-V semiconductor on a semiconductor substrate. The first conductivity type semiconductor material continuously extending along an entirety of the semiconductor substrate in a plurality of triangular shaped islands; and conformally forming a layer of type III-V semiconductor material having a second conductivity type on the plurality of triangular shaped islands.
    Type: Grant
    Filed: December 7, 2017
    Date of Patent: July 13, 2021
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Ning Li, Devendra K. Sadana, Ghavam G. Shahidi
  • Patent number: 11056722
    Abstract: A solid state electrochemical battery fabrication device and a method of creating the solid state electrochemical battery are provided. There is a first chamber comprising a first magnetron and a second chamber comprising a second magnetron, coupled to the first chamber. There is a third chamber comprising a vapor source for a polymer deposition, coupled to the second chamber. A Knudsen cell is coupled to the third chamber and configured to deposit lithium on a battery being fabricated. A linear hollow shaft connects the first, second, and third chambers, and provides a hermetic seal. A first telescopic arm having a housing is coupled to a first end of the hollow shaft and configured to extend out of its housing from the first chamber to the second chamber.
    Type: Grant
    Filed: February 8, 2018
    Date of Patent: July 6, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Frank Robert Libsch, Ghavam G. Shahidi, Ko-Tao Lee, Stephen M. Rossnagel
  • Patent number: 11023208
    Abstract: A true random number generator includes a latch circuit, a noise circuit coupled to the latch circuit and an equalization circuit coupled to the inputs of the latch circuit, the equalization circuit being configured to maintain the latch circuit in a balanced state and to allow the latch circuit to resolve from a metastable state based on a timing control. A method of generating a random number output includes maintaining a latch circuit in a balanced state by turning on an equalization circuit coupled to the inputs of the latch circuit, coupling at least one noise source to the latch circuit, allowing the latch circuit to resolve from a metastable state by turning off the equalization circuit and repeatedly turning the equalization circuit on and off based on a timing control.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: June 1, 2021
    Assignee: International Business Machines Corporation
    Inventors: Chitra K. Subramanian, Ghavam G. Shahidi
  • Patent number: 11024754
    Abstract: A photovoltaic device that includes a p-n junction of first type III-V semiconductor material layers, and a window layer of a second type III-V semiconductor material on the light receiving end of the p-n junction, wherein the second type III-V semiconductor material has a greater band gap than the first type III-V semiconductor material, and the window layer of the photovoltaic device has a cross-sectional area of microscale.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: June 1, 2021
    Assignee: International Business Machines Corporation
    Inventors: Talia S. Gershon, Ning Li, Devendra K. Sadana, Ghavam G. Shahidi
  • Patent number: 11011662
    Abstract: Photovoltaic devices such as solar cells having one or more field-effect hole or electron inversion/accumulation layers as contact regions are configured such that the electric field required for charge inversion and/or accumulation is provided by the output voltage of the photovoltaic device or that of an integrated solar cell unit. In some embodiments, a power source may be connected between a gate electrode and a contact region on the opposite side of photovoltaic device. In other embodiments, the photovoltaic device or integrated unit is self-powering.
    Type: Grant
    Filed: January 6, 2019
    Date of Patent: May 18, 2021
    Assignee: International Business Machines Corporation
    Inventors: Bahman Hekmatshoartabari, Devendra K. Sadana, Wilfried E. Haensch, Ghavam G. Shahidi, Davood Shahrjerdi
  • Patent number: 10997321
    Abstract: A private key of a public-private key pair with a corresponding identity is written to an integrated circuit including a processor, a non-volatile memory, and a cryptographic engine coupled to the processor and the non-volatile memory. The private key is written to the non-volatile memory. The integrated circuit is implemented in complementary metal-oxide semiconductor 14 nm or smaller technology. The integrated circuit is permanently modified, subsequent to the writing, such that further writing to the non-volatile memory is disabled and such that the private key can be read only by the cryptographic engine and not off-chip. Corresponding integrated circuits and wafers are also disclosed.
    Type: Grant
    Filed: September 21, 2019
    Date of Patent: May 4, 2021
    Assignee: International Business Machines Corporation
    Inventors: Richard H. Boivie, Eduard A. Cartier, Daniel J. Friedman, Kohji Hosokawa, Charanjit Jutla, Wanki Kim, Chandrasekara Kothandaraman, Chung Lam, Frank R. Libsch, Seiji Munetoh, Ramachandran Muralidhar, Vijay Narayanan, Dirk Pfeiffer, Devendra K. Sadana, Ghavam G. Shahidi, Robert L. Wisnieff
  • Patent number: 10957596
    Abstract: A method for fabricating caterpillar trenches for wafer dicing includes forming at least one opening within a mask formed on a substrate to protect an electronics device disposed on the substrate during isotropic etching, and isotropically etching through the at least one opening to form at least one wafer dicing channel, including laterally etching a collection of nested trenches including trenches each having a non-circular cross-section from a first surface of the substrate to a second surface of the substrate opposite the first surface.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: March 23, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Effendi Leobandung, Ghavam G. Shahidi
  • Patent number: 10957252
    Abstract: A pixel circuit includes a first transistor, a second transistor connected to a first source/drain of the first transistor, a circuit element connected to a gate of the first transistor and ground and configured to receive a select input and maintain the select input less than or equal to a potential of the ground, and a resistive element connected to an organic light emitting diode (OLED) and a first source/drain of the second transistor.
    Type: Grant
    Filed: August 15, 2019
    Date of Patent: March 23, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bahman Hekmatshoartabari, Ghavam G. Shahidi
  • Patent number: 10957806
    Abstract: A method of forming a photovoltaic device that includes epitaxially growing a first conductivity type semiconductor material of a type III-V semiconductor on a semiconductor substrate. The first conductivity type semiconductor material continuously extending along an entirety of the semiconductor substrate in a plurality of triangular shaped islands; and conformally forming a layer of type III-V semiconductor material having a second conductivity type on the plurality of triangular shaped islands.
    Type: Grant
    Filed: April 13, 2017
    Date of Patent: March 23, 2021
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Ning Li, Devendra K. Sadana, Ghavam G. Shahidi
  • Patent number: 10916629
    Abstract: A semiconductor structure that occupies only one areal device area is provided that includes a charge storage region sandwiched between a pFET nanosheet device and an nFET nanosheet device. The charge storage region is an epitaxial oxide nanosheet that is lattice matched to an underlying first silicon channel material nanosheet and an overlying second silicon channel material nanosheet. The semiconductor structure can be used as an EPROM device.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: February 9, 2021
    Assignee: International Business Machines Corporation
    Inventors: Alexander Reznicek, Jeng-Bang Yau, Tak H. Ning, Ghavam G. Shahidi
  • Patent number: 10910495
    Abstract: A method for manufacturing a semiconductor device includes forming a semiconductor layer on an insulating layer, epitaxially growing a first layer on the semiconductor layer, wherein the first layer has a first doping concentration, epitaxially growing a second layer on the semiconductor layer, wherein the second layer has a second doping concentration higher than the first doping concentration, forming a gate dielectric over an active region of the semiconductor layer, forming a gate electrode on the gate dielectric, and forming a plurality of source/drain contacts to the second layer, wherein the first and second layers comprise crystalline hydrogenated silicon (c-Si:H).
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: February 2, 2021
    Assignee: International Business Machines Corporation
    Inventors: Bahman Hekmatshoartabari, Ghavam G. Shahidi, Marinus P.J. Hopstaken
  • Patent number: 10903208
    Abstract: An electrical device including a plurality of fin structures. The plurality of fin structures including at least one decoupling fin and at least one semiconductor fin. The electrical device includes at least one semiconductor device including a channel region present in the at least one semiconductor fin, a gate structure present on the channel region of the at least one semiconductor fin, and source and drain regions present on source and drain region portion of the at least one semiconductor fin. The electrical device includes at least one decoupling capacitor including the decoupling fin structure as a first electrode of the decoupling capacitor, a node dielectric layer and a second electrode provided by the metal contact to the source and drain regions of the semiconductor fin structures. The decoupling capacitor is present underlying the power line to the semiconductor fin structures.
    Type: Grant
    Filed: January 10, 2020
    Date of Patent: January 26, 2021
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Ali Khakifirooz, Darsen D. Lu, Ghavam G. Shahidi
  • Patent number: 10875351
    Abstract: The present invention provides a method and a structure of electrical component assembly on flexible materials. In an exemplary embodiment, the method and the structure include patterning metal on a tape, creating one or more holes in the tape, attaching one or more electronic devices to the tape in the one or more holes such that a profile of the tape and the one or more electronic devices is less than a threshold, electrically connecting the one or more electronic devices to the patterned metal, cutting the tape, resulting in one or more component portions of the tape and one or more excess portions of the tape, where the one or more component portions comprises at least one of the one or more electronic devices, attached to the patterned metal, and bonding the one or more component portions to a ribbon.
    Type: Grant
    Filed: June 18, 2019
    Date of Patent: December 29, 2020
    Assignee: International Business Machines Corporation
    Inventors: Frank R. Libsch, Ghavam G. Shahidi
  • Patent number: 10879568
    Abstract: A method for forming a thin film lithium ion battery includes, under a same vacuum seal, forming a stack of layers on a substrate including an anode layer, an electrolyte, a cathode layer and a first cap over the stack of layers to protect the layers from air. Under a same vacuum seal, the stack of layers is etched with a non-reactive etch process in accordance with a hardmask, and a second cap layer is formed over the stack of layers without breaking the vacuum seal. Contacts coupled to the cathode and the anode are formed.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: December 29, 2020
    Assignee: International Business Machines Corporation
    Inventors: Effendi Leobandung, Ghavam G. Shahidi
  • Patent number: 10804366
    Abstract: A method is presented for forming a semiconductor device. The method may include forming a first gate structure on a first portion of a semiconductor material located on a surface of an insulating substrate, the first gate structure including a first sacrificial layer and a second sacrificial layer and forming a second gate structure on a second portion of the semiconductor material located on the surface of the insulating substrate, the second gate structure including a third sacrificial layer. The method further includes etching the first and second dielectric sacrificial layers to create a first contact region within the first gate structure and etching the third dielectric sacrificial layer to create a second contact region within the second gate structure. The method further includes forming silicide in at least the first and second contact regions of the first and second gate structures, respectively.
    Type: Grant
    Filed: June 18, 2019
    Date of Patent: October 13, 2020
    Assignee: ELPIS TECHNOLOGIES INC.
    Inventors: Bahman Hekmatshoartabari, Ghavam G. Shahidi
  • Patent number: 10772720
    Abstract: High resolution active matrix nanowire circuits enable a flexible platform for artificial electronic skin having pressure sensing capability. Comb-like interdigitated nanostructures extending vertically from a pair of opposing, flexible assemblies facilitate pressure sensing via changes in resistance caused by varying the extent of contact among the interdigitated nanostructures. Electrically isolated arrays of vertically extending, electrically conductive nanowires or nanofins are formed from a doped, electrically conductive layer, each of the arrays being electrically connected to a transistor in an array of transistors. The nanowires or nanofins are interdigitated with further electrically conductive nanowires or nanofins mounted to a flexible handle.
    Type: Grant
    Filed: May 12, 2018
    Date of Patent: September 15, 2020
    Assignee: International Business Machines Corporation
    Inventors: Bahman Hekmatshoartabari, Ghavam G. Shahidi, Davood Shahrjerdi
  • Patent number: 10770614
    Abstract: A method of forming an electrical device that includes epitaxially growing a first conductivity type semiconductor material of a type III-V semiconductor on a semiconductor substrate. The first conductivity type semiconductor material continuously extending along an entirety of the semiconductor substrate in a plurality of triangular shaped islands; and conformally forming a layer of type III-V semiconductor material having a second conductivity type on the plurality of triangular shaped islands to provide a textured surface of a photovoltaic device. A light emitting diode is formed on the textured surface of the photovoltaic device.
    Type: Grant
    Filed: April 23, 2019
    Date of Patent: September 8, 2020
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Ning Li, Devendra K. Sadana, Ghavam G. Shahidi
  • Patent number: 10763386
    Abstract: A photovoltaic device that includes an upper cell that absorbs a first range of wavelengths of light and a bottom cell that absorbs a second range of wavelengths of light. The bottom cell includes a heterojunction comprising a crystalline germanium containing (Ge) layer. At least one surface of the crystalline germanium (Ge) containing layer is in contact with a silicon (Si) containing layer having a larger band gap than the crystalline (Ge) containing layer.
    Type: Grant
    Filed: July 13, 2018
    Date of Patent: September 1, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Keith E. Fogel, Bahman Hekmatshoartabari, Devendra K. Sadana, Ghavam G. Shahidi, Davood Shahrjerdi
  • Publication number: 20200259658
    Abstract: A processor-implemented method imposes trust at the edge of a blockchain. A hardware interrogator in a terminal interrogates an Internet of Things Smart Device (IoTSD). The IoTSD is an off-line device that is associated with a physical product. The IoTSD includes a cryptographic processor and one or more state sensors that monitor a state of the physical product. The hardware interrogator detects an event that is described by an encrypted entry in the IoTSD. The terminal transmits, to a blockchain, a transaction that describes the event that is detected by the hardware interrogator, such that the blockchain adds the transaction to a blockchain that is dedicated to the physical product, and the blockchain establishes a state of the physical product.
    Type: Application
    Filed: February 7, 2019
    Publication date: August 13, 2020
    Inventors: FRANK R. LIBSCH, SEIJI MUNETOH, ABHILASH NARENDRA, GHAVAM G. SHAHIDI
  • Publication number: 20200251336
    Abstract: A hard mask and a method of creating thereof are provided. A first layer is deposited that is configured to provide at least one of a chemical and a mechanical adhesion to a layer immediately below it. A second layer is deposited having an etch selectivity that is faster than the first layer. A third layer is deposited having an etch selectivity that is slower than the first and second layers. The third layer has a composite strength that is higher than the first and second layers. A photoresist layer is deposited on top of the third layer and chemically removed above an inner opening. The third layer and part of the second layer are anisotropically etched through the inner opening. The second layer and the first layer are isotropically etched to create overhang regions of the third layer.
    Type: Application
    Filed: April 18, 2020
    Publication date: August 6, 2020
    Inventors: Frank Robert Libsch, Ghavam G. Shahidi, Ko-Tao Lee, Stephen M. Rossnagel