Abstract: A pixel circuit includes a circuit element connected to a gate of a first transistor and ground, which receives a select input. A data line is coupled to a first source/drain of the first transistor, and a second source/drain of the first transistor is coupled to a gate of a second transistor. The second transistor has a drain connected to a supply voltage and a source connected to a resistive element. The resistive element connects to an organic light emitting diode (OLED), which connects to the ground.

Abstract: An electrical device that includes a material stack present on a supporting substrate. An LED is present in a first end of the material stack having a first set of bandgap materials. A photovoltaic device is present in a second end of the material stack having a second set of bandgap materials. The first end of the material stack being a light receiving end, wherein a widest bandgap material for the first set of bandgap material is greater than a highest bandgap material for the second set of bandgap materials. A zinc oxide interface layer is present between the LED and the photovoltaic device. The zinc oxide layers or can also form a LED.

Abstract: A method for fabricating caterpillar trenches for wafer dicing includes forming at least one opening within a mask formed on a substrate to protect an electronics device disposed on the substrate during isotropic etching, and isotropically etching through the at least one opening to form at least one wafer dicing channel, including laterally etching a collection of nested trenches including trenches each having a non-circular cross-section from a first surface of the substrate to a second surface of the substrate opposite the first surface.

Abstract: A method for fabricating caterpillar trenches for wafer dicing includes forming at least one opening from a top surface of a mask formed on a substrate to a bottom surface of the mask opposite the top surface of the mask. The mask is formed on the substrate to protect an electronics device disposed on the substrate during isotropic etching. The method further includes isotropically etching through the at least one opening to form at least one wafer dicing channel, including isotropically etching a collection of nested trenches from a top surface of the substrate to a bottom surface of the substrate opposite the top surface of the substrate.

Abstract: A method for fabricating caterpillar trenches for wafer dicing includes forming at least one opening from a top surface of a mask formed on a substrate to a bottom surface of the mask opposite the top surface of the mask. The mask is formed on the substrate to protect an electronics device disposed on the substrate during isotropic etching. The method further includes isotropically etching through the at least one opening to form at least one wafer dicing channel, including isotropically etching a collection of nested trenches from a top surface of the substrate to a bottom surface of the substrate opposite the top surface of the substrate.

Abstract: A complementary circuit, including a logic unit comprising pull-up depletion-mode MOS transistors and pull-down depletion-mode MOS transistors having a single channel type and a level shifting circuit coupled to the logic unit.

Abstract: A complementary circuit, including a logic unit which includes pull-up depletion-mode MOS transistors and pull-down depletion-mode MOS transistors and a level shifting circuit coupled to the logic unit.

Abstract: An apparatus includes a junction field-effect transistor (JFET) and a set of one or more serially-connected diodes. The JFET includes a first layer including silicon of a first conductivity type, a gate, and first and second terminals. The gate includes a second layer formed on the first layer and including intrinsic amorphous hydrogenated silicon, a third layer formed on the second layer and including amorphous hydrogenated silicon of a second conductivity type, and a conductive layer formed on the third layer. Each of the first and second terminals includes a fourth layer formed on the first layer, the fourth layer including crystalline hydrogenated silicon of the first conductivity type, and a conductive layer formed on the fourth layer. Each of the serially-connected diodes has first and second terminals, a first of the serially-connected diodes having the first terminal connected to the second terminal of the JFET.

Abstract: A semiconductor structure that occupies only one areal device area is provided that includes a charge storage region sandwiched between a pFET nanosheet device and an nFET nanosheet device. The charge storage region is an epitaxial oxide nanosheet that is lattice matched to an underlying first silicon channel material nanosheet and an overlying second silicon channel material nanosheet. The semiconductor structure can be used as an EPROM device.

Abstract: A method of forming a photovoltaic device that includes ion implanting a first conductivity type dopant into first regions of a semiconductor layer of an SOI substrate, wherein the first regions are separated by a first pitch; and ion implanting a second conductivity type dopant into second regions of the semiconductor layer of the SOI substrate. The second regions are separated by a second pitch. Each second conductivity type implanted region of the second regions is in direct contact with first conductivity type implanted region of the first regions to provide a plurality of p-n junctions, and adjacent p-n junctions are separated by an intrinsic portion of the semiconductor layer to provide P-I-N cells that are horizontally oriented.

Abstract: A photovoltaic device that includes a p-n junction of first type III-V semiconductor material layers, and a window layer of a second type III-V semiconductor material on the light receiving end of the p-n junction, wherein the second type III-V semiconductor material has a greater band gap than the first type III-V semiconductor material, and the window layer of the photovoltaic device has a cross-sectional area of microscale.

Abstract: A method for fabricating a device with integrated photovoltaic cells includes supporting a semiconductor substrate on a first handle substrate and doping the semiconductor substrate to form doped alternating regions with opposite conductivity. A doped layer is formed over a first side the semiconductor substrate. A conductive material is patterned over the doped layer to form conductive islands such that the conductive islands are aligned with the alternating regions to define a plurality of photovoltaic cells connected in series on a monolithic structure.

Abstract: A private key of a public-private key pair with a corresponding identity is written to an integrated circuit including a processor, a non-volatile memory, and a cryptographic engine coupled to the processor and the non-volatile memory. The private key is written to the non-volatile memory. The integrated circuit is implemented in complementary metal-oxide semiconductor 14 nm or smaller technology. The integrated circuit is permanently modified, subsequent to the writing, such that further writing to the non-volatile memory is disabled and such that the private key can be read only by the cryptographic engine and not off-chip. Corresponding integrated circuits and wafers are also disclosed.

Abstract: A private key of a public-private key pair with a corresponding identity is written to an integrated circuit including a processor, a non-volatile memory, and a cryptographic engine coupled to the processor and the non-volatile memory. The private key is written to the non-volatile memory. The integrated circuit is implemented in complementary metal-oxide semiconductor 14 nm or smaller technology. The integrated circuit is permanently modified, subsequent to the writing, such that further writing to the non-volatile memory is disabled and such that the private key can be read only by the cryptographic engine and not off-chip. Corresponding integrated circuits and wafers are also disclosed.

Abstract: Provided is a light emitting semiconductor structure that operates as a light emitting diode (LED). In embodiments of the invention, the light emitting semiconductor structure includes a first barrier region, a second barrier region, and a single quantum well having a preselected thickness between the first barrier region and the second barrier region. The preselected thickness according to embodiments is selected to achieve a predetermined charge density in the quantum well. The predetermined charge density according to embodiments results from a predetermined bias current applied to the semiconductor structure. The predetermined bias current according to embodiments comprises less than about 1 mA.

Abstract: A method for manufacturing a semiconductor device includes forming a semiconductor layer on an insulating layer, epitaxially growing a first layer on the semiconductor layer, wherein the first layer has a first doping concentration, epitaxially growing a second layer on the semiconductor layer, wherein the second layer has a second doping concentration higher than the first doping concentration, forming a gate dielectric over an active region of the semiconductor layer, forming a gate electrode on the gate dielectric, and forming a plurality of source/drain contacts to the second layer, wherein the first and second layers comprise crystalline hydrogenated silicon (c-Si:H).

Abstract: A photovoltaic device that includes a p-n junction of first type III-V semiconductor material layers, and a window layer of a second type III-V semiconductor material on the light receiving end of the p-n junction, wherein the second type III-V semiconductor material has a greater band gap than the first type III-V semiconductor material, and the window layer of the photovoltaic device has a cross-sectional area of microscale.

Abstract: A pixel circuit includes a first transistor, a second transistor connected to a first source/drain of the first transistor, a circuit element connected to a gate of the first transistor and ground and configured to receive a select input and maintain the select input less than or equal to a potential of the ground, and a resistive element connected to an organic light emitting diode (OLED) and a first source/drain of the second transistor.

Abstract: An apparatus includes a junction field-effect transistor (JFET) and a set of one or more serially-connected diodes. The JFET includes a first layer including silicon of a first conductivity type, a gate, and first and second terminals. The gate includes a second layer formed on the first layer and including intrinsic amorphous hydrogenated silicon, a third layer formed on the second layer and including amorphous hydrogenated silicon of a second conductivity type, and a conductive layer formed on the third layer. Each of the first and second terminals includes a fourth layer formed on the first layer, the fourth layer including crystalline hydrogenated silicon of the first conductivity type, and a conductive layer formed on the fourth layer. Each of the serially-connected diodes has first and second terminals, a first of the serially-connected diodes having the first terminal connected to the second terminal of the JFET.

Abstract: The present invention provides a method and a structure of electrical component assembly on flexible materials. In an exemplary embodiment, the method and the structure include patterning metal on a tape, creating one or more holes in the tape, attaching one or more electronic devices to the tape in the one or more holes such that a profile of the tape and the one or more electronic devices is less than a threshold, electrically connecting the one or more electronic devices to the patterned metal, cutting the tape, resulting in one or more component portions of the tape and one or more excess portions of the tape, where the one or more component portions comprises at least one of the one or more electronic devices, attached to the patterned metal, and bonding the one or more component portions to a ribbon.