Patents by Inventor Gil I. Winograd
Gil I. Winograd has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9542997Abstract: A system includes a memory block. The memory block includes a local control circuit that is operable to control a memory operation of the memory block. The local control circuit includes a local sense amplifier. The system also includes a global memory control circuit separate from the memory block, and the global memory control circuit is operable to communicate with the local control circuit. The global memory control circuit includes a global data latch operable to receive a sensed data state from the local sense amplifier.Type: GrantFiled: October 7, 2015Date of Patent: January 10, 2017Assignee: Broadcom CorporationInventors: Ali Anvar, Gil I. Winograd, Esin Terzioglu
-
Publication number: 20160027503Abstract: A system includes a memory block. The memory block includes a local control circuit that is operable to control a memory operation of the memory block. The local control circuit includes a local sense amplifier. The system also includes a global memory control circuit separate from the memory block, and the global memory control circuit is operable to communicate with the local control circuit. The global memory control circuit includes a global data latch operable to receive a sensed data state from the local sense amplifier.Type: ApplicationFiled: October 7, 2015Publication date: January 28, 2016Inventors: Ali Anvar, Gil I. Winograd, Esin Terzioglu
-
Patent number: 9214208Abstract: A decoder for decoding an address having a plurality of bits ranging from a first address bit a1 to a last address bit aN, each address bit being either true or false is provided that includes a pre-charge circuit adapted to pre-charge a dynamic NOR node and a dynamic OR node and then allow the pre-charged dynamic NOR node and pre-charged dynamic OR node to float; a plurality of switches coupled between the dynamic NOR node and ground, each switch corresponding uniquely to the address bits such that the switches range from a first switch corresponding to a1 to an nth switch corresponding to aN, wherein any switch corresponding to a true address bit is configured to turn on only if its corresponding address bit is false, and wherein any switch corresponding to a false address bit is configured to turn on only if its corresponding address bit is true.Type: GrantFiled: October 14, 2014Date of Patent: December 15, 2015Assignee: Mentor Graphics CorporationInventors: Esin Terzioglu, Gil I. Winograd
-
Patent number: 9159385Abstract: A system includes a memory block. The memory block includes a local control circuit that is operable to control a memory operation of the memory block. The local control circuit includes a local sense amplifier. The system also includes a global memory control circuit separate from the memory block, and the global memory control circuit is operable to communicate with the local control circuit. The global memory control circuit includes a global sense amplifier operable to receive a sensed data state from the local sense amplifier.Type: GrantFiled: January 14, 2014Date of Patent: October 13, 2015Assignee: Broadcom CorporationInventors: Ali Anvar, Gil I. Winograd, Esin Terzioglu
-
Publication number: 20150162062Abstract: A decoder for decoding an address having a plurality of bits ranging from a first address bit a1 to a last address bit aN, each address bit being either true or false is provided that includes a pre-charge circuit adapted to pre-charge a dynamic NOR node and a dynamic OR node and then allow the pre-charged dynamic NOR node and pre-charged dynamic OR node to float; a plurality of switches coupled between the dynamic NOR node and ground, each switch corresponding uniquely to the address bits such that the switches range from a first switch corresponding to a1 to an nth switch corresponding to aN, wherein any switch corresponding to a true address bit is configured to turn on only if its corresponding address bit is false, and wherein any switch corresponding to a false address bit is configured to turn on only if its corresponding address bit is true.Type: ApplicationFiled: October 14, 2014Publication date: June 11, 2015Applicant: MENTOR GRAPHICS CORPORATIONInventors: Esin Terzioglu, Gil I. Winograd
-
Patent number: 8861302Abstract: A decoder for decoding an address having a plurality of bits ranging from a first address bit a1 to a last address bit aN, each address bit being either true or false is provided that includes a pre-charge circuit adapted to pre-charge a dynamic NOR node and a dynamic OR node and then allow the pre-charged dynamic NOR node and pre-charged dynamic OR node to float; a plurality of switches coupled between the dynamic NOR node and ground, each switch corresponding uniquely to the address bits such that the switches range from a first switch corresponding to a1 to an nth switch corresponding to aN, wherein any switch corresponding to a true address bit is configured to turn on only if its corresponding address bit is false, and wherein any switch corresponding to a false address bit is configured to turn on only if its corresponding address bit is true.Type: GrantFiled: August 7, 2013Date of Patent: October 14, 2014Assignee: Mentor Graphics CorporationInventors: Esin Terzioglu, Gil I. Winograd
-
Publication number: 20140126314Abstract: A system includes a memory block. The memory block includes a local control circuit that is operable to control a memory operation of the memory block. The local control circuit includes a local sense amplifier. The system also includes a global memory control circuit separate from the memory block, and the global memory control circuit is operable to communicate with the local control circuit. The global memory control circuit includes a global sense amplifier operable to receive a sensed data state from the local sense amplifier.Type: ApplicationFiled: January 14, 2014Publication date: May 8, 2014Applicant: Broadcom CorporationInventors: Ali Anvar, Gil I. Winograd, Esin Terzioglu
-
Patent number: 8693279Abstract: A system includes a memory block and a controller. The controller is adapted to skew a pre-charge signal for a bit line of the memory block. The controller can skew the pre-charge signal during a read operation or a write operation. The system can also include a sense amplifier in communication with a bit line of the memory block, and the sense amplifier can automatically shut off after indicating a sensed data state for the bit line. The controller may be a global controller or a local controller.Type: GrantFiled: February 18, 2013Date of Patent: April 8, 2014Assignee: Broadcom CorporationInventors: Ali Anvar, Gil I. Winograd, Esin Terzioglu
-
Publication number: 20130321028Abstract: A decoder for decoding an address having a plurality of bits ranging from a first address bit a1 to a last address bit aN, each address bit being either true or false is provided that includes a pre-charge circuit adapted to pre-charge a dynamic NOR node and a dynamic OR node and then allow the pre-charged dynamic NOR node and pre-charged dynamic OR node to float; a plurality of switches coupled between the dynamic NOR node and ground, each switch corresponding uniquely to the address bits such that the switches range from a first switch corresponding to a1 to an nth switch corresponding to aN, wherein any switch corresponding to a true address bit is configured to turn on only if its corresponding address bit is false, and wherein any switch corresponding to a false address bit is configured to turn on only if its corresponding address bit is true.Type: ApplicationFiled: August 7, 2013Publication date: December 5, 2013Applicant: Mentor Graphics CorporationInventors: Esin Terzioglu, Gil I. Winograd
-
Patent number: 8379478Abstract: The present invention relates to a system and method for adjusting timing of memory access operations to a memory block. In one embodiment, a controller may be in communication with a memory block. The controller may be adapted to adjust timing of a memory access operation to the memory block by extending a portion of a clock pulse to compensate for delay associated with the memory block. The delay may correspond to a predecoder delay or a global decoder delay. The clock pulse may be a read clock pulse or a write clock pulse. In one embodiment, the controller may be adapted to adjust timing of a read clock pulse differently from a write clock pulse.Type: GrantFiled: March 30, 2012Date of Patent: February 19, 2013Assignee: Broadcom CorporationInventors: Ali Anvar, Gil I. Winograd, Esin Terzioglu
-
Publication number: 20120235707Abstract: A decoder for decoding an address having a plurality of bits ranging from a first address bit a1 to a last address bit aN, each address bit being either true or false is provided that includes a pre-charge circuit adapted to pre-charge a dynamic NOR node and a dynamic OR node and then allow the pre-charged dynamic NOR node and pre-charged dynamic OR node to float; a plurality of switches coupled between the dynamic NOR node and ground, each switch corresponding uniquely to the address bits such that the switches range from a first switch corresponding to a1 to an nth switch corresponding to aN, wherein any switch corresponding to a true address bit is configured to turn on only if its corresponding address bit is false, and wherein any switch corresponding to a false address bit is configured to turn on only if its corresponding address bit is true.Type: ApplicationFiled: November 14, 2011Publication date: September 20, 2012Inventors: Esin Terzioglu, Gil I. Winograd
-
Publication number: 20120185664Abstract: The present invention relates to a system and method for adjusting timing of memory access operations to a memory block. In one embodiment, a controller may be in communication with a memory block. The controller may be adapted to adjust timing of a memory access operation to the memory block by extending a portion of a clock pulse to compensate for delay associated with the memory block. The delay may correspond to a predecoder delay or a global decoder delay. The clock pulse may be a read clock pulse or a write clock pulse.Type: ApplicationFiled: March 30, 2012Publication date: July 19, 2012Applicant: BROADCOM CORPORATIONInventors: Ali Anvar, Gil I. Winograd, Esin Terzioglu
-
Patent number: 8149645Abstract: The present invention relates to a system and method for processing the read and write operations in a memory architecture. The system processing the read and write operations includes at least one local memory block and a synchronously controlled global controller coupled to the local memory block and adapted to extend the high portion of a clock pulse. The method for processing the read and write operations includes skewing a clock pulse using at least one word line interfacing with the global controller.Type: GrantFiled: March 30, 2010Date of Patent: April 3, 2012Assignee: Broadcom CorporationInventors: Ali Anvar, Gil I. Winograd, Esin Terzioglu
-
Patent number: 8004912Abstract: The present invention relates to a system and method for providing redundancy in a hierarchically memory, by replacing small blocks in such memory. The present invention provides such redundancy (i.e., replaces such small blocks) by either shifting predecoded lines or using a modified shifting predecoder circuit in the local predecoder block. In one embodiment, the hierarchal memory structure includes at least one active predecoder adapted to be shifted out of use; and at least one redundant predecoder adapted to be shifted in to use.Type: GrantFiled: June 25, 2009Date of Patent: August 23, 2011Assignee: Broadcom CorporationInventors: Esin Terzioglu, Gil I. Winograd, Morteza Cyrus Afghahi
-
Publication number: 20110141840Abstract: A decoder for decoding an address having a plurality of bits ranging from a first address bit a1 to a last address bit aN, each address bit being either true or false is provided that includes a pre-charge circuit adapted to pre-charge a dynamic NOR node and a dynamic OR node and then allow the pre-charged dynamic NOR node and pre-charged dynamic OR node to float; a plurality of switches coupled between the dynamic NOR node and ground, each switch corresponding uniquely to the address bits such that the switches range from a first switch corresponding to a1 to an nth switch corresponding to aN, wherein any switch corresponding to a true address bit is configured to turn on only if its corresponding address bit is false, and wherein any switch corresponding to a false address bit is configured to turn on only if its corresponding address bit is true; a (n+1)th switch coupling the dynamic OR node to ground, the (n+1)th switch being controlled such that it turns on if the dynamic OR node is charged, whereby theType: ApplicationFiled: December 14, 2010Publication date: June 16, 2011Applicant: NOVELICS, LLC.Inventors: Esin Terzioglu, Gil I. Winograd
-
Patent number: 7903497Abstract: In one embodiment, a multi-port SRAM is provided that comprises: a single input port and output port 6-T SRAM; and a multi-port control block circuit that includes: a plurality of input registers corresponding to a plurality of input ports to register corresponding input signals; an input multiplexer to select from the input registers to provide a selected input signal to the 6-T SRAM's single input port; a plurality of output registers corresponding to a plurality of output ports to register corresponding output signals; and an output de-multiplexer to select from the output registers to provide an output signal from the 6-T SRAM's single output port to the selected output register.Type: GrantFiled: October 24, 2008Date of Patent: March 8, 2011Assignee: Novelics, LLCInventors: Esin Terzioglu, Gil I. Winograd, Andreas Gotterba
-
Patent number: 7889553Abstract: A non-volatile memory cell includes: a substrate including diffusion regions for a read-out transistor; a capacitor formed in a poly-silicon layer adjacent the substrate, the capacitor including a floating gate for the read-out transistor and a control gate, the floating gate and the control gate each having finger extensions, the finger extensions from the floating gate interdigitating with the finger extensions from the control gate; and a programming line coupled to the control gate.Type: GrantFiled: April 24, 2008Date of Patent: February 15, 2011Assignee: Novelics, LLC.Inventors: Esin Terzioglu, Gil I. Winograd, Morteza Cyrus Afghahi
-
Patent number: 7852113Abstract: In one embodiment, a leakage reduction circuit is provided that includes: a virtual power supply node; a first PMOS transistor coupled between the virtual power supply node and a power supply node; a second PMOS transistor having a source coupled to the power supply node; and a native NMOS transistor coupled between a drain of the second PMOS transistor and the virtual power supply node, the native NMOS transistor having a gate driven by the power supply node.Type: GrantFiled: December 1, 2008Date of Patent: December 14, 2010Assignee: Novelics, LLC.Inventors: Esin Terzioglu, Gil I. Winograd
-
Patent number: 7852688Abstract: In one embodiment, a memory includes: an array of memory cells arranged according to word lines and columns, each column corresponding to bit lines; a sense amplifier adapted to couple to the bit lines to sense a binary content of selected cells from the array of memory cells, the sense amplifier sensing the binary content responsive to a sense command; an x-decoder configured to assert a selected one of the word lines in response to decoding an address as triggered by a clock edge, wherein the assertion of the selected word line switches on corresponding access transistors to develop voltages on the bit lines; and a bit line replica circuit adapted to replicate the development of the bit lines, the bit line replica circuit including a replica access transistor coupled between a replica bit line and a replica memory cell wherein the replica access transistor is switched on responsive to the clock edge such that the replica memory cell pulls the replica bit line to ground, the bit line replica circuit also incType: GrantFiled: April 23, 2008Date of Patent: December 14, 2010Assignee: Novelics, LLC.Inventors: Esin Terzioglu, Gil I. Winograd
-
Patent number: 7782697Abstract: In one embodiment, a hybrid DRAM is provided that includes: a sense amplifier including a differential amplifier and regenerative latch, wherein the differential amplifier and regenerative latch are constructed using core transistors; and a plurality of memory cells coupled to the sense amplifier through a pair of bit lines, wherein the memory cells are constructed using I/O transistors.Type: GrantFiled: August 27, 2007Date of Patent: August 24, 2010Assignee: Novelics, LLC.Inventors: Esin Terzioglu, Gil I. Winograd, Melinda L. Miller