Patents by Inventor Gil I. Winograd
Gil I. Winograd has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20080083942Abstract: A non-volatile memory cell includes a floating gate transistor having a floating gate coupled to a metal layer capacitor defined in one or more metal layers. Within each metal layer, the metal layer capacitor includes a first plate coupled to the floating gate and a second plate separated from the first plate by a fringe capacitance junction.Type: ApplicationFiled: September 28, 2006Publication date: April 10, 2008Inventors: Esin Terzioglu, Gil I. Winograd, Morteza Cyrus Afghahi
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Publication number: 20080074915Abstract: A one-time-programmable memory cell uses two complementary antifuses that are programmed in a complementary fashion such that only one of the two complementary antifuses is stressed by a programming voltage. The programming voltage stress one a particular one of the complementary antifuses indicates a logical state of the memory cell. For example, a logical high state may correspond to a first one of the complementary antifuses being stressed whereas a logical low state may correspond to the stressing of the remaining one of the complementary antifuses.Type: ApplicationFiled: May 11, 2007Publication date: March 27, 2008Inventors: Esin Terzioglu, Gil I. Winograd, Morteza Cyrus Afghahi
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Patent number: 7271615Abstract: In one embodiment, NMOS transistors have their source coupled to a common source node such that the NMOS transistors conduct a leakage current if the common source node is grounded. To reduce this leakage current, the common source node is raised in potential. Similarly, PMOS transistors have their source coupled to a common source node such that the PMOS transistors conduct a leakage current if the common source node is charged to a power supply voltage VDD. To reduce this leakage current, the common source node is lowered in potential.Type: GrantFiled: December 12, 2005Date of Patent: September 18, 2007Assignee: Novelics, LLCInventors: Morteza Afghahi, Esin Terzioglu, Gil I. Winograd
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Patent number: 7260020Abstract: The present invention relates to a system and method for processing the read and write operations in a memory architecture. The system processing the read and write operations includes at least one local memory block and a synchronously controlled global controller coupled to the local memory block and adapted to extend the high portion of a clock pulse. The method for processing the read and write operations includes skewing a clock pulse using at least one word line interfacing with the global controller.Type: GrantFiled: July 28, 2005Date of Patent: August 21, 2007Assignee: Broadcom CorporationInventors: Ali Anvar, Gil I. Winograd, Esin Terzioglu
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Patent number: 7230872Abstract: The present invention relates to a system and method adapted to increase memory cell and memory architecture design yield. The present invention includes memory architecture having a decoder and a multi-bank memory. The decoder is adapted to decode addresses. The multi-bank memory interacts with the decoder, wherein the multi-bank memory includes at least one output data bit adapted to complete a word for a failing bank in the multi-bank memory.Type: GrantFiled: February 23, 2005Date of Patent: June 12, 2007Assignee: Broadcom CorporationInventors: Gil I. Winograd, Esin Terzioglu
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Patent number: 7221577Abstract: The present invention relates to a system and method for equalizing the capacitance between/among n lines of a bus running in parallel for a portion of their length. The system and method include determining a twisting pattern for the n lines using an algorithm for example. After determining the twisting pattern forming at least n?1 twisted sections, the n lines are twisted according to the pattern so that each of the n lines runs along every other line for a same distance across the length of a bus.Type: GrantFiled: May 24, 2004Date of Patent: May 22, 2007Assignee: Broadcom CorporationInventors: Gil I. Winograd, Bibhudatta Sahoo, Esin Terzioglu
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Patent number: 7177225Abstract: The present invention relates to a system and method for providing redundancy in a hierarchically memory, by replacing small blocks in such memory. The present invention provides such redundancy (i.e., replaces such small blocks) by either shifting predecoded lines or using a modified shifting predecoder circuit in the local predecoder block. In one embodiment, the hierarchal memory structure includes at least one redundant predecoder adapted to be shifted in for at least one active predecoder of a plurality of predecoders adapted to be shifted out.Type: GrantFiled: December 5, 2003Date of Patent: February 13, 2007Assignee: Broadcom CorporationInventors: Esin Terzioglu, Gil I. Winograd, Cyrus Afghahi
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Patent number: 7154810Abstract: The present invention relates to a synchronous self timed memory device. The device includes a plurality of memory cells forming a cell array, at least one local decoder interfacing with the cell array, at least one local sense amplifier and at least one local controller. The local sense amplifier interfaces with at least the decoder and cell array, and is adapted to precharge and equalize at least one line coupled thereto. The local controller interfaces with and coordinates the activities of at least the local decoder and sense amplifier.Type: GrantFiled: January 31, 2005Date of Patent: December 26, 2006Assignee: Broadcom CorporationInventors: Gil I. Winograd, Esin Terzioglu, Ali Anvar, Sami Issa
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Patent number: 7095248Abstract: The present invention relates to a system and method for increasing the manufacturing yield of a plurality of memory cells used in cell arrays. A programmable fuse, having both hardware and software modes, is used with the plurality of memory cells to indicate that at least one memory cells is unusable and should be shifted out of operation. The software mode comprises a software programmable element adapted to shift in an appropriate value indicating that at least one of the memory cells is flawed. The hardware mode comprises a hardware element adapted to indicate the at least one memory cell is unusable and is gated with the software programmable element. The hardware and software modes act autonomously.Type: GrantFiled: September 13, 2004Date of Patent: August 22, 2006Assignee: Broadcom CorporationInventors: Esin Terzioglu, Gil I. Winograd
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Patent number: 7054212Abstract: A digital memory system (30) includes a memory cell (52), a bit line (50), a transfer gate (60) a reference voltage generator (40), a sense amplifier (70) and a control circuit (80). The control circuit precharges the bit line to a bit line precharge voltage, which is sampled and stored. A corresponding reference voltage is generated after the bit line is isolated. The bit line and reference voltage are coupled to the sense amplifier so that a voltage is received based on charge stored in the memory cell. The sense amplifier then is isolated from the bit line and reference voltage and the sense amplifier is energized so that an output voltage is derived from the charge and reference voltage.Type: GrantFiled: January 25, 2005Date of Patent: May 30, 2006Assignee: Broadcom CorporationInventors: Esin Terzioglu, Morteza Cyrus Afghahi, Gil I. Winograd
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Patent number: 6990020Abstract: A non-volatile memory cell (10) includes a charge-storing node (16). An electrically insulating first layer (76) is coupled between the node and a source of a first voltage (22). An electrically insulating second layer (66) is coupled between the node and a source of a second voltage (20–21). The area of the first layer is smaller than the area of the second layer. A controller (90) is arranged to cause the first voltage to be greater than the second voltage so that charge is extracted from the node and is arranged to cause the second voltage to be greater than the first voltage so that charge is injected into the node.Type: GrantFiled: November 8, 2004Date of Patent: January 24, 2006Assignee: Broadcom CorporationInventors: Esin Terzioglu, Morteza Cyrus Afghahi, Gil I. Winograd
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Patent number: 6970382Abstract: In a digital memory system, systems and methods that control a logical value and an integrity of data represented by charge are provided. In one embodiment, a bit line is coupled to the cell. A voltage generator is arranged to generate a plurality of cell operating voltages varying in response to a voltage control signal. A controller generates a control signal, stores a predetermined one of logical values in a cell by generating a series of operating voltages, transmits the series of operating voltages, and determines whether the predetermined one of the logical values has been stored in the cell in response to a voltage on the bit line. The controller includes a charge integrity estimating module and determines whether the predetermined one of the logical values has been stored in the cell by initiating the operation of the charge integrity estimating module.Type: GrantFiled: December 29, 2004Date of Patent: November 29, 2005Assignee: Broadcom CorporationInventors: Zeynep Toros, Esin Terzioglu, Ahmad O. Siksek, Gil I. Winograd, Ali Anvar
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Patent number: 6947350Abstract: The present invention relates to a synchronous self timed memory device. The device includes a plurality of memory cells forming a cell array, at least one local decoder interfacing with the cell array, at least one local sense amplifier and at least one local controller. The local sense amplifier interfaces with at least the decoder and cell array, and is adapted to precharge and equalize at least one line coupled thereto. The local controller interfaces with and coordinates the activities of at least the local decoder and sense amplifier. One embodiment of the present invention relates to a memory device comprising a plurality of synchronous controlled global elements and a plurality of self-timed local elements. In this embodiment, at least one of the self-timed local elements interfaces with the synchronous controlled global element.Type: GrantFiled: November 12, 2003Date of Patent: September 20, 2005Assignee: Broadcom CorporationInventors: Gil I. Winograd, Esin Terzioglu, Ali Anvar, Sami Issa
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Patent number: 6928026Abstract: The present invention relates to a system and method for processing the read and write operations in a memory architecture. The system processing the read and write operations includes at least one local memory block and a synchronously controlled global controller coupled to the local memory block and adapted to extend the high portion of a clock pulse. The method for processing the read and write operations includes skewing a clock pulse using at least one word line interfacing with the global controller.Type: GrantFiled: June 21, 2002Date of Patent: August 9, 2005Assignee: Broadcom CorporationInventors: Ali Anvar, Gil I. Winograd, Esin Terzioglu
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Patent number: 6909648Abstract: A system and method for applying a stress to a hierarchical memory structure in parallel, testing the memory structure for weak defects. The system and method includes writing a logic 0 into all the memory cells in a memory structure. All the high address predecoded lines and alternating predecoded lines for the lowest address are enabled. A voltage drop between neighboring wordlines and bitlines is affected. A logic 1 is written into all the memory cells in the memory structure. An opposite voltage polarity is caused on the bitlines due to the logic 1 in the memory cells. A reverse voltage polarity stress is achieved on the wordlines by flipping the state of the lowest predecoded line (i.e., by changing the input address corresponding to that line.Type: GrantFiled: March 19, 2002Date of Patent: June 21, 2005Assignee: Broadcom CorporationInventors: Esin Terzioglu, Gil I. Winograd
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Patent number: 6901019Abstract: A digital memory system (30) includes a memory cell (52), a bit line (50), a transfer gate (60) a reference voltage generator (40), a sense amplifier (70) and a control circuit (80). The control circuit precharges the bit line to a bit line precharge voltage, which is sampled and stored. A corresponding reference voltage is generated after the bit line is isolated. The bit line and reference voltage are coupled to the sense amplifier so that a voltage is received based on charge stored in the memory cell. The sense amplifier then is isolated from the bit line and reference voltage and the sense amplifier is energized so that an output voltage is derived from the charge and reference voltage.Type: GrantFiled: May 26, 2004Date of Patent: May 31, 2005Assignee: Broadcom CorporationInventors: Esin Terzioglu, Morteza Cyrus Afghahi, Gil I. Winograd
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Patent number: 6898145Abstract: The present invention relates to a system and method for providing distributed, highly configurable modular predecoding. The method comprising forming a hierarchical memory structure including forming a first portion of the hierarchical memory structure adapted to perform a first layer of address predecoding. The method further comprises forming a second portion of the hierarchical memo structure interacting with at least the first portion and adapted to perform a second layer of address predecoding.Type: GrantFiled: May 10, 2004Date of Patent: May 24, 2005Assignee: Broadcom CorporationInventors: Gil I. Winograd, Esin Terzioglu, Cyrus Afghahi, Ali Anvar, Sami Issa
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Patent number: 6898663Abstract: In one aspect, the invention describes a mechanism for refreshing multiple memory words (rows) per refresh cycle, the number of simultaneously refreshed rows being programmable by a small number of inputs. In another aspect, the invention discloses a mechanism for refreshing all banks or a programmable number of banks simultaneously in a multi-bank memory. In yet another aspect, the present invention describes a mechanism for refreshing a programmable multiple memory rows and a programmable multiple banks simultaneously.Type: GrantFiled: August 12, 2003Date of Patent: May 24, 2005Assignee: Broadcom CorporationInventors: Gil I. Winograd, Sami Issa, Morteza Cyrus Afghahi
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Patent number: 6894231Abstract: The present invention relates to a system and method for equalizing the capacitance between at least two lines of a bus running in parallel for a portion of their length. The system and method include determining a twisting pattern for the lines using an algorithm. After determining the twisting pattern, the lines are twisted according to the pattern so that each of the lines runs along every other line for a same distance across the length of the bus.Type: GrantFiled: March 19, 2002Date of Patent: May 17, 2005Assignee: Broadcom CorporationInventors: Gil I. Winograd, Bibhudatta Sahoo, Esin Terzioglu
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Patent number: 6882591Abstract: The present invention relates to a synchronous self timed memory device. The device includes a plurality of memory cells forming a cell array, at least one local decoder interfacing with the cell array, at least one local sense amplifier and at least one local controller. One embodiment relates to a memory device comprising a muxing device and at least one cluster device coupled to the muxing device. Another embodiment comprises a method of performing at least one of a read and write operation in a memory device. The method comprises activating at least one cluster device in the memory device and firing at least one sense amp in the at least one cluster device.Type: GrantFiled: October 23, 2003Date of Patent: April 19, 2005Assignee: Broadcom CorporationInventors: Gil I. Winograd, Esin Terzioglu, Ali Anvar, Sami Issa