Patents by Inventor Gilberto Curatola
Gilberto Curatola has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20190081039Abstract: A first semiconductor body including type IV semiconductor material is provided. A second semiconductor body including type III-V semiconductor material is provided. A first adhesion layer is formed on the first semiconductor body. A second adhesion layer is formed on the second semiconductor body. The first and the second semiconductor bodies are bonded together by adhering the first and the second adhesion layers to one another.Type: ApplicationFiled: September 14, 2017Publication date: March 14, 2019Inventors: Ralf Siemieniec, Daniel Kueck, Gilberto Curatola, Romain Esteve
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Patent number: 10204995Abstract: A heterostructure body with a buffer region, and a barrier region disposed on the buffer region is provided. A gate trench is formed in the barrier region. A layer of doped semiconductor material that fills the gate trench is formed. The doped semiconductor material in the gate trench locally depletes a subjacent section of the two-dimensional charge carrier gas channel at zero bias. A layer of electrically conductive material is formed on the doped semiconductor material. The layer of doped semiconductor material is structured to form a gate structure that includes a narrower portion of the doped semiconductor material that is disposed in the gate trench, a wider portion of the doped semiconductor material that is above the trench, and a gate electrode portion of the electrically conductive material that completely covers the wider portion of the doped semiconductor material.Type: GrantFiled: November 28, 2016Date of Patent: February 12, 2019Assignee: Infineon Technologies Austria AGInventors: Simone Lavanga, Marco Silvestri, Gilberto Curatola
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Patent number: 10153362Abstract: In an embodiment, a semiconductor device includes an enhancement mode Group III-nitride-based High Electron Mobility Transistor (HEMT) including a drain, a gate, a barrier layer, a channel layer, a barrier layer arranged on the channel layer, and a heterojunction formed between the barrier layer and the channel layer and capable of supporting a two-dimensional electron gas (2DEG). At least one of a thickness and a composition of the barrier layer is configured to decrease a 2DEG density in a channel region compared with a 2DEG density outside of the channel region, wherein the channel region is arranged under the gate and extends a distance d beyond a drain-sided gate edge.Type: GrantFiled: October 27, 2016Date of Patent: December 11, 2018Assignee: Infineon Technologies Austria AGInventors: Gilberto Curatola, Oliver Haeberlen
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Patent number: 10074597Abstract: The disclosure is directed to techniques to evenly distribute current in interdigited leadframes by decoupling current between interdigited pads. The leadframe may use a perpendicular structure between the leadframe conductive pads and the lead traces. The perpendicular structure provides a short path for the current to travel from electrode pad openings on a device to the lead traces carrying current to other portions of a circuit. The conductive pad may be parallel to the electrode pad opening to lower spreading resistance. In an example of a transistor, the transistor may have two or more electrode pads for every current carrying node. Therefore, several electrode pads may have the same node, such as the source or drain of the device. For example, two or more source pads may be connected though the leadframe to evenly distribute the current and decouple the current from a single transistor.Type: GrantFiled: January 20, 2017Date of Patent: September 11, 2018Assignee: Infineon Technologies Austria AGInventors: Eung San Cho, Oliver Haeberlen, Klaus Schiess, Gilberto Curatola, Gerhard Prechtl
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Patent number: 10038085Abstract: A method includes providing a heterostructure body with a buffer region, and a barrier region disposed on the buffer region, and forming a gate structure for controlling the channel on the heterostructure body, the gate structure having a doped semiconductor region disposed on the heterostructure body, an interlayer disposed on the doped semiconductor region, and a gate electrode disposed on the interlayer. Forming the gate structure includes controlling a doping concentration of the doped semiconductor region such that a portion of the channel adjacent the gate structure is non-conductive at zero gate bias, and controlling electrical and geometrical characteristics of the interlayer based upon a relationship between the electrical and geometrical characteristics of the interlayer and corresponding effects on a static threshold voltage and a dynamic threshold voltage shift of the semiconductor device.Type: GrantFiled: January 8, 2016Date of Patent: July 31, 2018Assignee: Infineon Technologies Austria AGInventors: Gilberto Curatola, Oliver Haeberlen, Gerhard Prechtl, Clemens Ostermaier
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Publication number: 20180211904Abstract: The disclosure is directed to techniques to evenly distribute current in interdigited leadframes by decoupling current between interdigited pads. The leadframe may use a perpendicular structure between the leadframe conductive pads and the lead traces. The perpendicular structure provides a short path for the current to travel from electrode pad openings on a device to the lead traces carrying current to other portions of a circuit. The conductive pad may be parallel to the electrode pad opening to lower spreading resistance. In an example of a transistor, the transistor may have two or more electrode pads for every current carrying node. Therefore, several electrode pads may have the same node, such as the source or drain of the device. For example, two or more source pads may be connected though the leadframe to evenly distribute the current and decouple the current from a single transistor.Type: ApplicationFiled: January 20, 2017Publication date: July 26, 2018Applicant: Infineon Technologies Americas Corp.Inventors: Eung San Cho, Oliver Haeberlen, Klaus Schiess, Gilberto Curatola, Gerhard Prechtl
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Publication number: 20180204915Abstract: A semiconductor device includes a base layer, a dielectric layer over the base layer, an opening extending through the dielectric layer and to a main surface of the base layer, the opening having a sloped sidewall, and an electrically conductive material over the sloped sidewall. An angle between the sloped sidewall and the main surface of the base layer is in a range between 5 degrees and 50 degrees. Corresponding methods of manufacturing the semiconductor device are also provided.Type: ApplicationFiled: January 19, 2017Publication date: July 19, 2018Inventors: Jens Ulrich Heinle, Gerhard Prechtl, Gilberto Curatola
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Publication number: 20180151681Abstract: A heterostructure body with a buffer region, and a barrier region disposed on the buffer region is provided. A gate trench is formed in the barrier region. A layer of doped semiconductor material that fills the gate trench is formed. The doped semiconductor material in the gate trench locally depletes a subjacent section of the two-dimensional charge carrier gas channel at zero bias. A layer of electrically conductive material is formed on the doped semiconductor material. The layer of doped semiconductor material is structured to form a gate structure that includes a narrower portion of the doped semiconductor material that is disposed in the gate trench, a wider portion of the doped semiconductor material that is above the trench, and a gate electrode portion of the electrically conductive material that completely covers the wider portion of the doped semiconductor material.Type: ApplicationFiled: November 28, 2016Publication date: May 31, 2018Inventors: Simone Lavanga, Marco Silvestri, Gilberto Curatola
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Publication number: 20180138304Abstract: A semiconductor device includes a type III-V semiconductor body having a main surface and a rear surface opposite the main surface. A barrier region is disposed beneath the main surface. A buffer region is disposed beneath the barrier region. A first two-dimensional charge carrier gas region forms near an interface between the barrier region and the buffer region. A second two-dimensional charge carrier gas region forms near an interface between the buffer region and the first back-barrier region. A third two-dimensional charge carrier gas region forms near an interface between the first back-barrier region and the second back-barrier region. Both of the second and third two-dimensional charge carrier gas regions have an opposite carrier type as the first two-dimensional charge carrier gas region. The third two-dimensional charge carrier gas region is more densely populated with charge carriers than the second two-dimensional charge carrier gas region.Type: ApplicationFiled: November 15, 2016Publication date: May 17, 2018Inventor: Gilberto Curatola
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Patent number: 9884715Abstract: A container for containing a perishable substance has a container wall with an inner side and an outer side. The wall has an electrically conductive layer extending between the inner side and the outer side. The inner side faces the space containing the substance. The container comprises electronic circuitry having a sensor for sensing a physical property or condition of the substance, and an antenna for communicating an RF signal to a receiver, external to the container. The RF signal is indicative of the physical property or condition sensed. The sensor is positioned so as to be exposed to the space containing the substance in operational use of the container. The antenna is positioned at the outer side, or between the outer side and the electrically conductive layer, and is electrically isolated from the electrically conductive layer.Type: GrantFiled: May 26, 2011Date of Patent: February 6, 2018Assignee: NXP B.V.Inventors: Romano Hoofman, Roel Daamen, Youri Victorovitch Ponomarev, Fotopoulou Kyriaki, Matthias Merz, Gilberto Curatola, Anton Tombeur
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Patent number: 9825139Abstract: A semiconductor device includes a device region including a compound semiconductor material and a non-device region at least partially surrounding the device region. The semiconductor device further includes a dielectric material in the non-device region and at least one electrode in the device region. The semiconductor device further includes at least one pad electrically coupled to the at least one electrode, wherein the at least one pad is arranged on the dielectric material in the non-device region.Type: GrantFiled: January 10, 2017Date of Patent: November 21, 2017Assignee: Infineon Technologies Austria AGInventors: Gilberto Curatola, Oliver Haeberlen, Simone Lavanga, Gianmauro Pozzovivo, Fabian Reiher
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Patent number: 9735141Abstract: A transistor device includes a compound semiconductor body, a drain disposed in the compound semiconductor body and a source disposed in the compound semiconductor body and spaced apart from the drain by a channel region. A gate is provided for controlling the channel region. The transistor device further includes a gate overvoltage protection device connected between the source and the gate, the gate overvoltage protection device including p-type and n-type silicon-containing semiconductor material.Type: GrantFiled: February 23, 2016Date of Patent: August 15, 2017Assignee: Infineon Technologies Austria AGInventors: Martin Vielemeyer, Michael Hutzler, Gilberto Curatola, Gianmauro Pozzovivo
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Publication number: 20170200817Abstract: A method includes providing a heterostructure body with a buffer region, and a barrier region disposed on the buffer region, and forming a gate structure for controlling the channel on the heterostructure body, the gate structure having a doped semiconductor region disposed on the heterostructure body, an interlayer disposed on the doped semiconductor region, and a gate electrode disposed on the interlayer. Forming the gate structure includes controlling a doping concentration of the doped semiconductor region such that a portion of the channel adjacent the gate structure is non-conductive at zero gate bias, and controlling electrical and geometrical characteristics of the interlayer based upon a relationship between the electrical and geometrical characteristics of the interlayer and corresponding effects on a static threshold voltage and a dynamic threshold voltage shift of the semiconductor device.Type: ApplicationFiled: January 8, 2016Publication date: July 13, 2017Inventors: Gilberto Curatola, Oliver Haeberlen, Gerhard Prechtl, Clemens Ostermaier
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Publication number: 20170148883Abstract: A semiconductor device includes a device region including a compound semiconductor material and a non-device region at least partially surrounding the device region. The semiconductor device further includes a dielectric material in the non-device region and at least one electrode in the device region. The semiconductor device further includes at least one pad electrically coupled to the at least one electrode, wherein the at least one pad is arranged on the dielectric material in the non-device region.Type: ApplicationFiled: January 10, 2017Publication date: May 25, 2017Inventors: Gilberto Curatola, Oliver Haeberlen, Simone Lavanga, Gianmauro Pozzovivo, Fabian Reiher
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Patent number: 9653591Abstract: A semiconductor device includes a first compound semiconductor material, a second compound semiconductor material on the first compound semiconductor material, the second compound semiconductor material having a first doping concentration and including a different material than the first compound semiconductor material, a control electrode, and at least one buried semiconductor material region having a second doping concentration different from the first doping concentration. The at least one buried semiconductor material region is disposed in the second compound semiconductor material in a region other than a region of the second compound semiconductor material being covered by the control electrode.Type: GrantFiled: July 29, 2015Date of Patent: May 16, 2017Assignee: Infineon Technologies Austria AGInventor: Gilberto Curatola
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Publication number: 20170125572Abstract: In an embodiment, a semiconductor device includes an enhancement mode Group III-nitride-based High Electron Mobility Transistor (HEMT) including a drain, a gate, a barrier layer, a channel layer, a barrier layer arranged on the channel layer, and a heterojunction formed between the barrier layer and the channel layer and capable of supporting a two-dimensional electron gas (2DEG). At least one of a thickness and a composition of the barrier layer is configured to decrease a 2DEG density in a channel region compared with a 2DEG density outside of the channel region, wherein the channel region is arranged under the gate and extends a distance d beyond a drain-sided gate edge.Type: ApplicationFiled: October 27, 2016Publication date: May 4, 2017Inventors: Gilberto Curatola, Oliver Haeberlen
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Patent number: 9570438Abstract: A semiconductor device includes a semiconductor body including first and second lateral surfaces. A first device region includes a drift region of a first conductivity type, and a drift current control region of a second conductivity type being spaced apart from the second lateral surface by the drift region. A second device region includes a barrier layer, and a buffer layer having a different band gap than the barrier layer so that a two-dimensional charge carrier gas channel arises along an interface between the buffer layer and the barrier layer. An electrically conductive substrate contact forms a low ohmic connection between the two-dimensional charge carrier gas channel and the drift region. A gate structure is configured to control a conduction state of the two-dimensional charge carrier gas. The drift current control region is configured to block a vertical current in the drift region via a space-charge region.Type: GrantFiled: August 4, 2015Date of Patent: February 14, 2017Assignee: Infineon Technologies Austria AGInventors: Gilberto Curatola, Ralf Siemieniec
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Publication number: 20170040312Abstract: A semiconductor device includes a semiconductor body including first and second lateral surfaces. A first device region includes a drift region of a first conductivity type, and a drift current control region of a second conductivity type being spaced apart from the second lateral surface by the drift region. A second device region includes a barrier layer, and a buffer layer having a different band gap than the barrier layer so that a two-dimensional charge carrier gas channel arises along an interface between the buffer layer and the barrier layer. An electrically conductive substrate contact forms a low ohmic connection between the two-dimensional charge carrier gas channel and the drift region. A gate structure is configured to control a conduction state of the two-dimensional charge carrier gas. The drift current control region is configured to block a vertical current in the drift region via a space-charge region.Type: ApplicationFiled: August 4, 2015Publication date: February 9, 2017Inventors: Gilberto Curatola, Ralf Siemieniec
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Patent number: 9564524Abstract: A semiconductor device includes a device region including a compound semiconductor material and a non-device region at least partially surrounding the device region. The semiconductor device further includes a dielectric material in the non-device region and at least one electrode in the device region. The semiconductor device further includes at least one pad electrically coupled to the at least one electrode, wherein the at least one pad is arranged on the dielectric material in the non-device region.Type: GrantFiled: May 28, 2015Date of Patent: February 7, 2017Assignee: Infineon Technologies Austria AGInventors: Gilberto Curatola, Oliver Haeberlen, Simone Lavanga, Gianmauro Pozzovivo, Fabian Reiher
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Publication number: 20170033210Abstract: A compound semiconductor device structure having a main surface and a rear surface includes a silicon substrate including first and second substrate layers. The first substrate layer extends to the rear surface. The second substrate layer extends to a first side of the substrate that is opposite from the rear surface such that the first substrate layer is completely separated from the first side by the second substrate layer. A nucleation region is formed on the first side of the silicon substrate and includes a nitride layer. A lattice transition layer is formed on the nucleation region and includes a type III-V semiconductor nitride. The lattice transition layer is configured to alleviate stress arising in the silicon substrate due to lattice mismatch between the silicon substrate and other layers in the compound semiconductor device structure. The second substrate layer is configured to suppress an inversion layer in the silicon substrate.Type: ApplicationFiled: July 31, 2015Publication date: February 2, 2017Inventors: Gilberto Curatola, Martin Huber, Ingo Daumiller