Patents by Inventor Gilberto Curatola
Gilberto Curatola has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20120086058Abstract: A tunnel field effect transistor and a method of making the same. The transistor includes a semiconductor substrate. The transistor also includes a gate located on a major surface of the substrate. The transistor further includes a drain of a first conductivity type. The transistor also includes a source of a second conductivity type extending beneath the gate. The source is separated from the gate by a channel region and a gate dielectric. The transistor is operable to allow charge carrier tunnelling from an inversion layer through an upper surface of the source.Type: ApplicationFiled: October 11, 2011Publication date: April 12, 2012Applicant: NXP B.V.Inventors: Gilberto Curatola, Dusan Golubovic, Johannes Josephus Theodorus Marinus Donkers, Guillaume Boccardi, Hans Mertens
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Publication number: 20110291806Abstract: A container for containing a perishable substance has a container wall with an inner side and an outer side. The wall has an electrically conductive layer extending between the inner side and the outer side. The inner side faces the space containing the substance. The container comprises electronic circuitry having a sensor for sensing a physical property or condition of the substance, and an antenna for communicating an RF signal to a receiver, external to the container. The RF signal is indicative of the physical property or condition sensed. The sensor is positioned so as to be exposed to the space containing the substance in operational use of the container. The antenna is positioned at the outer side, or between the outer side and the electrically conductive layer, and is electrically isolated from the electrically conductive layer.Type: ApplicationFiled: May 26, 2011Publication date: December 1, 2011Applicant: NXP B.V.Inventors: Romano Hoofman, Roel Daamen, Youri Victorovitch Ponomarev, Fotopoulou Kyriaki, Matthias Merz, Gilberto Curatola, Anton Tombeur
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Publication number: 20110241767Abstract: The invention describes a charge-pump circuit (1, 1?) comprising a supply voltage input node (10) for applying an input voltage (Uin) to be boosted, a boosted voltage output node (11) for outputting a boosted voltage (Uout), and a plurality of transistor stages connected in series between the supply voltage input node (10) and the boosted voltage output node (11), wherein at least one transistor stage comprises a multiple-gate transistor (D1, . . . , D5), which transistor (D1, . . . , D5) comprises at least two gates, of which one is a first gate (G) for switching the transistor (D1, . . . , D5) on or off according to a voltage applied to the first gate (G), and one is an additional second gate (Gi) for controlling the threshold voltage of the multiple-gate transistor (D1, . . . , D5), independently of the first gate (G), according to a control voltage (?1, ?2) applied to the second gate (Gi).Type: ApplicationFiled: December 17, 2009Publication date: October 6, 2011Applicant: NXP B.V.Inventors: Gilberto Curatola, Youri Victorovitch Ponomarev
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Publication number: 20110241103Abstract: A method of manufacturing a tunnel field effect transistor is disclosed. The method comprises forming a two-step profile in a silicon substrate (100) using a patterned hard mask (104) covering the higher steps of said profile; forming a gate stack (114, 116) against the side wall of the higher step; forming spacers (122) on either side of the gate stack (118); and implanting a first type impurity (124) in the higher step and an opposite type impurity in the neighboring lower step (120), wherein at least the first type impurity is implanted using an angled implanting step after removing the patterned hard mask (104). In a preferred embodiment, the method further comprises forming a sacrificial spacer (108) against a side wall of a higher step and the side wall of the hard mask (104); further etching the lower step (106, 110) next to said spacer (108) and subsequently growing a further semi-conductor portion (112) on said lower step and removing the spacer (108) prior to forming the gate stack.Type: ApplicationFiled: October 12, 2009Publication date: October 6, 2011Applicant: NXP B.V.Inventors: Gilberto Curatola, Marcus J.H. Van Dal
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Publication number: 20110208457Abstract: The invention relates to a method of determining a charged particle concentration in an analyte (100), the method comprising steps of: i) determining at least two measurement points of a surface-potential versus interface-temperature curve (c1, c2, c3, c4), wherein the interface temperature is obtained from a temperature difference between a first interface between a first ion-sensitive dielectric (Fsd) and the analyte (100) and a second interface between a second ion-sensitive dielectric (Ssd) and the analyte (100), and wherein the surface-potential is obtained from a potential difference between a first electrode (Fe) and a second electrode (Se) onto which said first ion-sensitive dielectric (Fsd) and said second ion-sensitive dielectric (Ssd) are respectively provided, And ii) calculating the charged particle concentration from locations of the at least two measurement points of said curve (c1, c2, c3, c4).Type: ApplicationFiled: August 24, 2009Publication date: August 25, 2011Applicant: NXP B.V.Inventors: Matthias Merz, Youri Victorovitch Ponomarev, Gilberto Curatola
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Patent number: 7923346Abstract: A method of making a FET includes forming a gate structure (18), then etching cavities on either side. A SiGe layer (22) is then deposited on the substrate (10) in the cavities, followed by an Si layer (24). A selective etch is then carried out to etch away the SiGe (22) except for a part of the layer under the gate structure (18), and oxide (28) is grown to fill the resulting gap. SiGe source and drains are then deposited in the cavities. The oxide (28) can reduce junction leakage current.Type: GrantFiled: December 7, 2006Date of Patent: April 12, 2011Assignee: NXP B.V.Inventors: Gilberto A. Curatola, Sebastien Nuttinck
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Publication number: 20110018065Abstract: A method of manufacturing a semiconductor device is disclosed comprising providing an insulating carrier (10) such as an oxide wafer; providing a channel structure (20) between a source structure (12) and a drain structure (14) on said carrier (10); selectively removing a part of the channel structure (20), thereby forming a recess (22) between the channel structure (20) and the carrier (10); exposing the device to an annealing step such that the channel structure (20?) obtains a substantially cylindrical shape; forming a confinement layer (40) surrounding the substantially cylindrical channel structure (20?); growing an oxide layer (50) surrounding the confinement layer (40); and forming a gate structure (60) surrounding the oxide layer (50). The substantially cylindrical channel structure 20? may comprise the semiconductor layer 30. A corresponding semiconductor device is also disclosed.Type: ApplicationFiled: February 17, 2009Publication date: January 27, 2011Applicant: NXP B.V.Inventors: Gilberto Curatola, Prabhat Agarwal, Mark J. H. Van Dal, Vijayaraghavan Madakasira
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Patent number: 7839209Abstract: A tunnel transistor includes source diffusion (4) of opposite conductivity type to a drain diffusion (6) so that a depletion layer is formed between source and drain diffusions in a lower doped region (8). An insulated gate (16) controls the position and thickness of the depletion layer. The device includes a quantum well formed in accumulation layer (20) which is made of a different material to the lower layer (2) and cap layer (22).Type: GrantFiled: October 3, 2007Date of Patent: November 23, 2010Assignee: NXP B.V.Inventors: Gilberto Curatola, Prabhat Agarwal, Jan W. Slotboom, Godefridus A. M. Hurkx, Radu Surdeanu, Gerben Doornbos
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Publication number: 20100097135Abstract: A tunnel transistor includes source diffusion (4) of opposite conductivity type to a drain diffusion (6) so that a depletion layer is formed between source and drain diffusions in a lower doped region (8). An insulated gate (16) controls the position and thickness of the depletion layer. The device includes a quantum well formed in accumulation layer (20) which is made of a different material to the lower layer (2) and cap layer (22).Type: ApplicationFiled: October 3, 2007Publication date: April 22, 2010Applicant: NXP, B.V.Inventors: Gilberto Curatola, Prabhat Agarwal, Jan W. Slotboom, Godefridus A.M. Hurkx, Radu Surdeanu
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Publication number: 20100066348Abstract: A detector device comprises a substrate (50), a source region (S) and a drain region (D), and a channel region (65) between the source and drain regions. A nanopore (54) passes through the channel region, and connects fluid chambers (56,58) on opposite sides of the substrate. A voltage bias is provided between the fluid chambers, the source and drain regions and a charge flow between the source and drain regions is sensed. The device uses a nanopore for the confinement of a sample under test (for example nucleotides) close to a sensor. The size of the sensor can be made similar to the spacing of adjacent nucleotides in a DNA strand. In this way, the disadvantages of PCR based techniques for DNA sequencing are avoided, and single nucleotide resolution can be attained.Type: ApplicationFiled: April 5, 2008Publication date: March 18, 2010Applicant: NXP B.V.Inventors: Matthias Merz, Youri V. Ponomarev, Gilberto Curatola
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Publication number: 20100044760Abstract: An impact ionisation MOSFET is formed with the offset from the gate to one of the source/drain regions disposed vertically within the device structure rather than horizontally. The semiconductor device comprises a first source/drain region having a first doping level; a second source/drain region having a second doping level and of opposite dopant type to the first source/drain region, the first and second source/drain regions being laterally separated by an intermediate region having a doping level less than either of the first and second doping levels; a gate electrode electrically insulated from, and disposed over, the intermediate region, the first and second source/drain regions being laterally aligned with the gate electrode; where the entire portion of the first source/drain region that forms a boundary with the intermediate region is separated vertically from the top of the intermediate region.Type: ApplicationFiled: November 13, 2007Publication date: February 25, 2010Applicant: NXP, B.V.Inventors: Gilberto Curatola, Mark Van Dal, Jan Sonsky
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Publication number: 20100025766Abstract: A transistor device (10), the transistor device (10) comprising a substrate (11, 14), a fin (3, 3A) aligned along a horizontal direction on the substrate (11, 14), a first source/drain region (4) of a first type of conductivity in the fin (3, 3A), a second source/drain region (5) of a second type of conductivity in the fin (3, 3A), wherein the first type of conductivity differs from the second type of conductivity, a channel region (33) in the fin (3, 3A) between the first source/drain region (4) and the second source/drain region (5), a gate insulator (6) on the channel region (33), and a gate structure (7, 8) on the gate insulator (6), wherein the sequence of the first source/drain region (4), the channel region (33) and the second source/drain region (5) is aligned along the horizontal direction.Type: ApplicationFiled: December 10, 2007Publication date: February 4, 2010Applicant: NXP, B.V.Inventors: Sebastien Nuttinck, Gilberto Curatola
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Publication number: 20090297938Abstract: A device is provided that includes a battery layer on a substrate, where a first battery cell is formed in the battery layer. The first battery cell includes a first anode, a first cathode, and a first electrolyte arranged between the first anode and the first cathode, where the first anode, the first cathode, and the first electrolyte are arranged in the battery layer such that perpendicular projections onto the substrate of each of the first anode and the first cathode are non-overlapping. A method of manufacturing such device is also provided. A system is also provide that includes such device for supplying power to an electronic device.Type: ApplicationFiled: May 28, 2009Publication date: December 3, 2009Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Romano HOOFMAN, Aurelie Humbert, Matthias Merz, Youri Victorovitch Ponomarev, Remco Henricus Wilhelmus Pijnenburg, Gilberto Curatola
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Publication number: 20090289298Abstract: An impact ionisation MOSFET is formed with the offset from the gate to one of the source/drain regions disposed vertically within the device structure rather than horizontally. The semiconductor device comprises a first source/drain region having a first doping level; a second source/drain region having a second doping level and of opposite dopant type to the first source/drain region, the first and second source/drain regions being laterally separated by a silicon-germanium intermediate region having a doping level less than either of the first and second doping levels; a gate electrode electrically insulated from, and disposed over, the intermediate region, the first and second source/drain regions being laterally aligned with the gate electrode; where the entire portion of the first source/drain region that forms a boundary with the intermediate region is separated vertically from the top of the intermediate region.Type: ApplicationFiled: April 28, 2009Publication date: November 26, 2009Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventor: Gilberto CURATOLA
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Publication number: 20090166761Abstract: A method of making a FET includes forming a gate structure (18), then etching cavities on either side. A SiGe layer (22) is then deposited on the substrate (10) in the cavities, followed by an Si layer (24). A selective etch is then carried out to etch away the SiGe (22) except for a part of the layer under the gate structure (18), and oxide (28) is grown to fill the resulting gap. SiGe source and drains are then deposited in the cavities. The oxide (28) can reduce junction leakage current.Type: ApplicationFiled: December 7, 2006Publication date: July 2, 2009Applicant: NXP B.V.Inventors: Gilberto A. Curatola, Sebastien Nuttinck
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Publication number: 20090159938Abstract: The invention relates to a method of manufacturing a semiconductor device (10) comprising a field effect transistor, in which method a semiconductor body of silicon (12) with a substrate (11) is provided at a surface thereof with a source region (1) and a drain region (2) of a first conductivity type which are situated above a buried isolation region (3,4) and with a channel region (5), between the source and drain regions (1,2), of a second conductivity type, opposite to the first conductivity type, and with a gate region (6) separated from the surface of the semiconductor body (12) by a gate dielectric (7) and situated above the channel region (5), and wherein a mesa (M) is formed in the semiconductor body (12) in which the channel region (5) is formed and wherein the source and drain regions (1,2) are formed on both sides of the mesa (M) in a semiconductor region (8) that is formed using epitaxial growth, the source and drain regions (1,2) thereby contacting the channel region (5).Type: ApplicationFiled: January 4, 2007Publication date: June 25, 2009Applicant: NXP B.V.Inventors: Sebastien Nuttinck, Gilberto Curatola, Erwin Hijzen, Philippe Meunier-Beillard
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Publication number: 20080277739Abstract: A fin FET array includes a number of fins 12 and a switch FET 52 between fins 12. The switch FET 52 acts to divide the transistor array into first 42 and second 44 FINFET regions having first 46 and second 48 gate electrodes controllably connected through the switch FET 52. Suitable voltages applied between the gate of the switch FET and the substrate 10 can allow the fin FET array either to act as a plurality of separate FETs or as a single device. A method of making the fin FET array to reduce the number of additional steps to fabricate the switch FET 52 is also described.Type: ApplicationFiled: October 10, 2006Publication date: November 13, 2008Applicant: NXP B.V.Inventor: Gilberto Curatola