Abstract: A solder joint or seal attaching components having dissimilar coefficients of thermal expansion is made thin (e.g., less than 20 ?m and preferably about 5 ?m) and of a solder such as an indium-based solder that has a tendency to creep. The solder is toroidal or otherwise shaped to avoid tensile stress in the solder. Axial shearing stress in the solder causes reversible creep without causing failure of the joint or seal. In one embodiment, a toroidal solder seal has a diameter, a footprint, and a thickness in approximate proportions of 5000:200:1.

Abstract: An elongated strip of a sheetlike substrate bearing microelectronic elements such as semiconductor chips is advanced in a downstream direction through one or more folding stations where successive portions of the substrate are folded so as to form a strip including a plurality of fold packages, each including confronting top and bottom runs and a fold region with one or more of the runs bearing one or more microelectronic elements. The strip incorporating the plural fold packages can be wound on a reel or otherwise handled, stored and shipped to a subsequent manufacturing operation, where individual fold packages can be severed from the strip.

Abstract: Various embodiments of packaged chips and ways of fabricating them are disclosed herein. One such packaged chip disclosed herein includes a chip having a front face, a rear face opposite the front face, and a device at one of the front and rear faces, the device being operable as a transducer of at least one of acoustic energy and electromagnetic energy, and the chip including a plurality of bond pads exposed at one of the front and rear faces. The packaged chip includes a package element having a dielectric element and a metal layer disposed on the dielectric element, the package element having an inner surface facing the chip and an outer surface facing away from the chip. The metal layer includes a plurality of contacts exposed at at least one of the inner and outer surfaces, the contacts conductively connected to the bond pads.

Abstract: Various embodiments of packaged chips and ways of fabricating them are disclosed herein. One such packaged chip disclosed herein includes a chip having a front face, a rear face opposite the front face, and a device at one of the front and rear faces, the device being operable as a transducer of at least one of acoustic energy and electromagnetic energy, and the chip including a plurality of bond pads exposed at one of the front and rear faces. The packaged chip includes a package element having a dielectric element and a metal layer disposed on the dielectric element, the package element having an inner surface facing the chip and an outer surface facing away from the chip. The metal layer includes a plurality of contacts exposed at at least one of the inner and outer surfaces, the contacts conductively connected to the bond pads.

Abstract: A microelectronic package includes a mounting structure, a microelectronic element associated with the mounting structure, and a plurality of conductive posts physically connected to the mounting structure and electrically connected to the microelectronic element. The conductive posts project from the mounting structure in an upward direction, at least one of the conductive posts being an offset post. Each offset post has a base connected to the mounting structure, the base of each offset post defining a centroid. Each offset post also defines an upper extremity having a centroid, the centroid of the upper extremity being offset from the centroid of the base in a horizontal offset direction transverse to the upward direction. The mounting structure is adapted to permit tilting of each offset post about a horizontal axis so that the upper extremities may wipe across a contact pad of an opposing circuit board.

Abstract: According to one aspect of the invention, a capped chip is provided which includes a chip having a front surface, a back surface opposite the front surface and a plurality of bond pads exposed at at least one of the front and back surfaces. A cap is joined to the chip, the cap overlying one of the front and back surfaces of the chip. The cap includes a plurality of contacts which are conductively interconnected to the bond pads, and one or more temporary ties which conductively connect two or more of the contacts. The temporary ties are severable after the contacts are conductively interconnected to the bond pads.

Abstract: An article is provided which includes a structure overlying a face of an element. The structure includes a first metal layer and a wettable metal layer overlying the first metal layer. A conductive trace overlies and contacts at least one of the first metal layer and the wettable metal layer, the trace having a composition different from at least one of the first metal layer and the wettable metal layer.

Abstract: Capped chips and methods of forming a capped chip are provided in which electrical interconnects are made by conductive elements which extend from bond pads of a chip at least partially through a plurality of through holes of a cap. The electrical interconnects may be solid, so as to form seals extending across the through holes. In some cases, stud bumps extend from the bond pads, forming parts of the electrical interconnects. In some cases, a fusible conductive medium forms a part of the electrical interconnects.

Abstract: A packaged microelectronic device is provided which includes: (a) a unit having a chip with an upwardly-facing front surface and a downwardly-facing rear surface, a lid overlying at least a portion of the front surface of the chip, the lid having a top surface facing upwardly away from the chip and unit connections exposed at the top surface of the lid. At least some of the unit connections are electrically connected to the chip. The packaged microelectronic device also includes a package structure including structure defining package terminals, at least some of the package terminals being electrically connected to the chip. The package structure, the unit or both define a downwardly-facing bottom surface of the package, the terminals being exposed at the bottom surface.

Abstract: A method of making a chip assembly is provided which includes the steps of: (a) assembling (i) a capped chip including a chip, a cap overlying a front surface of the chip and a sacrificial layer overlying the cap with (ii) one or more further components; and (b) after the assembling step, removing the sacrificial layer from the capped chip. A method of making a plurality of capped chip assemblies is provided which includes the steps of: (a) assembling a lid member and a chip member including a plurality of chips to one another so that the lid member overlies the chip member and a top surface of the lid member faces away from the chip member; (b) severing the lid member and chip member to form a plurality of individual units each including one or more of the chips and a portion of the lid member; (c) providing a sacrificial layer overlying the top surface of the lid member prior to the severing step; and (d) removing the sacrificial layer after the severing step.

Abstract: A method of making the lidded chip assembly are provided which includes the steps of: (a) aligning a lid member with a chip member including one or more chips so that electrically conductive elements projecting from a front surface of the chip-member extend into through-holes in the lid member and at least partially control location of the lid member relative to the chip member in one or more horizontal directions parallel to the front surface; and (b) forming interconnections extending through the lid member so that the interconnections include the conductive elements. A capped chip is provided in which the conductive interconnects extend from the chip through openings in a cap member, the openings being tapered to become smaller in a direction from the bottom or inner surface of the opening towards the top or outer surface.

Abstract: A method of making a plurality of sealed assemblies is provided which includes a) assembling a first element to a second element so that a bottom surface of the first element faces downwardly toward a front surface of the second element and a top surface of the first element faces upwardly away from the second element; and (b) forming ring seals surrounding regions of the front surface of the second element by introducing flowable material between the first element and the second element from the top surface of the first element through openings in the first element. A chip is provided which includes: (a) a body defining a front surface and one or more circuit elements on or within the body; (b) one or more bond pads exposed at the front surface in a bond pad region; and (c) a metallic ring exposed at the front surface, the ring substantially surrounding the bond pad region. Sealed chip assemblies are formed by sealing an array of the chips, e.g., in wafer form, to a cap element.

Abstract: A capped chip is provided which includes a chip and a cap member, the chip having a front surface and a plurality of bond pads exposed at the front surface, the cap member having a bottom surface facing the front surface of the chip and having a top surface opposite the front surface. A plurality of through holes extend from the bottom surface of the cap member to the top surface. The capped chip assembly further includes a plurality of metallic interconnects extending from the bond pads at least partially through the through holes, the metallic interconnects including stud bumps joined to the bond pads, the stud bumps contacting and engaging at least one of (i) the top surface of the cap member surrounding the through holes and (ii) inner surfaces of the through holes.

Abstract: A covered chip having an optical element integrated in the cover is provided which includes a chip having a front surface, an optically active circuit area, and bond pads disposed at the front surface. The chip is covered by an at least partially optically translucent or transparent unitary cover that is mounted to the front surface of the chip, and has at least one optical element integrated in the unitary cover. The cover is further aligned with the optically active circuit area and vertically spaced from the optically active circuit area.

Abstract: In a method of soldering the surfaces of a component (11) to a substrate (12), a solder preform (15) is located in the gap between the surfaces. The solder is heated and an over pressure applied to move the surfaces together whilst the solder is molten. Abutments (17) between the surfaces limit the spacing between them. A trapped void (18) is decreased in volume as the pressure is applied. The method is particularly applicable to monolithic microwave integrated circuits (MMIC) and reduces void areas in joints.

Abstract: Fluxless soldering processes use pressure variations and vented cavities within large-area solder joints to reduce void volumes and improve the properties of the large-area solder joints. The vents can be sealed after soldering if closed cavities are desired. A cavity can also improve hermeticity of a solder joint by providing an additional solder fillet around the cavity in addition to the solder fillet around the perimeter of the solder joint.

Abstract: A remote device such as a control value (4) is powered and controlled by optical energy, supplied by an intensity-modulated light source (8) and optical fibre (10). After conversion into electrical form, the light is detected at (12) and applied to a piezoelectric transformer (14). The output of the transformer powers and control an actuator (16) of the control value.

Abstract: A solder joint or seal attaching components having dissimilar coefficients of thermal expansion is made thin (e.g., less than 20 &mgr;m and preferably about 5 &mgr;m) and of a solder such as an indium-based solder that has a tendency to creep. The solder is toroidal or otherwise shaped to avoid tensile stress in the solder. Axial shearing stress in the solder causes reversible creep without causing failure of the joint or seal. In one embodiment, a toroidal solder seal has a diameter, a footprint, and a thickness in approximate proportions of 5000:200:1.

Abstract: Fluxless soldering processes use pressure variations and vented cavities within large-area solder joints to reduce void volumes and improve the properties of the large-area solder joints. The vents can be sealed after soldering if closed cavities are desired. A cavity can also improve hermeticity of a solder joint by providing an additional solder fillet around the cavity in addition to the solder fillet around the perimeter of the solder joint.

Abstract: A housing for a microwave circuit is formed from a base made of metal matrix composite material and walls made of sheet metal. The base and the walls are joined together by diffusion soldering. Some holes to receive feedthroughs are formed at the junction of the base and a wall.