Patents by Inventor Girish Dixit
Girish Dixit has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 5491355Abstract: A polycrystalline silicon layer is deposited and patterned to define a level of interconnect. Contact opening to lower conductive layers are then defined and patterned. A refractory metal such as tungsten is selectively deposited over the device, so that it adheres to the polycrystalline silicon in the interconnect leads and silicon of the lower conductive layer which is exposed in the contact openings. This provides a low resistance interconnect, and good, metal, contacts to underlying layers. Shared contacts between two or more polycrystalline silicon interconnect layers and in underlying conductive layers such as a substrate are easily formed using this technique.Type: GrantFiled: July 23, 1993Date of Patent: February 13, 1996Assignee: SGS-Thomson Microelectronics, Inc.Inventors: Che C. Wei, Chiara Zaccherini, Robert O. Miller, Girish A. Dixit
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Patent number: 5444019Abstract: A method is provided for forming an integrated circuit contact structure. A conductive region is formed on a semiconductor device. Thereafter an insulating layer is formed over the conductive region. An opening is then formed through the insulating region to the conductive region. A thin barrier layer is deposited over the integrated circuit contact structure. A portion of the thin barrier layer is removed by backsputtering the integrated circuit contact structure so that only a thin barrier sidewall remains. Finally, a conductive metal layer is deposited over the integrated circuit contact structure. In one embodiment, the integrated circuit contact structure is baked before the conductive metal layer is deposited.Type: GrantFiled: November 24, 1993Date of Patent: August 22, 1995Assignee: SGS-Thomson Microelectronics, Inc.Inventors: Fusen E. Chen, Girish A. Dixit, Che-Chia Wei
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Patent number: 5440166Abstract: A field oxide structure is formed within a cavity formed in a semiconductor substrate. The cavity has a U-shaped cross section. A layer of thermal oxide covers the walls and bottom of the cavity, and a region of reflowable glass or spin on glass fills the cavity. A layer of undoped oxide, having an upper surface coplanar with the substrate upper surface is formed over the cavity, so that the spin on or reflowable glass is completely surrounded by either thermal oxide or an undoped oxide layer.Type: GrantFiled: July 15, 1994Date of Patent: August 8, 1995Assignee: SGS-Thomson Microelectronics, Inc.Inventors: Girish A. Dixit, Fusen E. Chen, Robert O. Miller
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Patent number: 5391520Abstract: A method for fabrication of local interconnects in an integrated circuit, and an integrated circuit formed according to the same, is disclosed. According to the disclosed embodiment, a first and a second conductive structure are formed over the integrated circuit. An insulating layer is formed over the integrated. A first photoresist layer is formed over the insulating layer, patterned and developed. The insulating layer is etched to expose selected regions of the first and second conductive structures. A refractory metal layer is formed over the integrated circuit. A barrier layer is formed over the refractory metal layer, and optionally a refractory metal silicide layer is formed over the barrier layer. A second photoresist layer is formed over the barrier layer, patterned and developed.Type: GrantFiled: October 18, 1993Date of Patent: February 21, 1995Assignee: SGS-Thomson Microelectronics, Inc.Inventors: Fusen Chen, Fu-Tai Liou, Girish Dixit
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Patent number: 5369302Abstract: The method for fabrication of semiconductor contacts resulting in rounded contact corners providing for increased step coverage includes depositing a glass layer over a substrate and heating the glass layer to reflow. The glass layer is patterned and etched to form a contact opening. A barrier layer is deposited, annealed, and selectively wet etched leaving the barrier layer only in the bottom of the contact opening. The glass layer is reflowed again to form rounded contact corners.Type: GrantFiled: February 21, 1992Date of Patent: November 29, 1994Assignee: SGS-Thomson Microelectronics, Inc.Inventors: Fusen E. Chen, Girish A. Dixit
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Patent number: 5348901Abstract: A method is provided for forming a polycrystalline silicon resistive load element of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A lightly doped first conductive layer having a conductivity of a first type. A first oxide layer is formed over the integrated circuit with a first opening therethrough exposing a portion of the first conductive layer. Using the first oxide layer as a mask, the exposed portion of the first conductive layer is then implanted with a dopant of a second conductivity type to form a junction between the exposed portion and the portion covered by the mask. A second oxide region is then formed on a portion of the first oxide layer in the first opening, over the junction and over a portion of the exposed first conductive layer adjacent to the junction. A silicide is formed over the exposed portion of the first conductive layer.Type: GrantFiled: July 9, 1992Date of Patent: September 20, 1994Assignee: SGS-Thomson Microelectronics, Inc.Inventors: Fusen E. Chen, Girish A. Dixit, Robert O. Miller
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Patent number: 5319245Abstract: A method for fabrication of local interconnects in an integrated circuit, and an integrated circuit formed according to the same, is disclosed. According to the disclosed embodiment, a first and a second conductive structure are formed over the integrated circuit. An insulating layer is formed over the integrated. A first photoresist layer is formed over the insulating layer, patterned and developed. The insulating layer is etched to expose selected regions of the first and second conductive structures. A refractory metal layer is formed over the integrated circuit. A barrier layer is formed over the refractory metal layer, and optionally a refractory metal silicide layer is formed over the barrier layer. A second photoresist layer is formed over the barrier layer, patterned and developed.Type: GrantFiled: November 23, 1992Date of Patent: June 7, 1994Assignee: SGS-Thomson Microelectronics, Inc.Inventors: Fusen Chen, Fu-Tai Liou, Girish Dixit
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Patent number: 5317192Abstract: A method is provided for forming an integrated circuit contact structure. A conductive region is formed on a semiconductor device. Thereafter an insulating layer is formed over the conductive region. An opening is then formed through the insulating region to the conductive region. A thin barrier layer is deposited over the integrated circuit contact structure. A portion of the thin barrier layer is removed by backsputtering the integrated circuit contact structure so that only a thin barrier sidewall remains. Finally, a conductive metal layer is deposited over the integrated circuit contact structure. In one embodiment, the integrated circuit contact structure is baked before the conductive metal layer is deposited.Type: GrantFiled: May 6, 1992Date of Patent: May 31, 1994Assignee: SGS-Thomson Microelectronics, Inc.Inventors: Fusen E. Chen, Girish A. Dixit, Che-Chia Wei
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Patent number: 5285103Abstract: The method for fabrication of openings in semiconductor devices to improve metal step coverage includes forming an active region over a substrate. A metal oxide layer is then formed over the source/drain region. An insulating layer is formed over the metal oxide layer. A photoresist layer is formed over the insulating layer, and patterned to form an opening, exposing a portion of the insulating. The insulating layer is then etched to expose a portion of the metal oxide layer. The photoresist layer is removed and the insulating layer is reflowed so as to form rounded corners at the opening of the insulating layer. The exposed portion of the metal oxide layer is removed to expose a portion of the active region.Type: GrantFiled: April 7, 1992Date of Patent: February 8, 1994Assignee: SGS-Thomson Microelectronics, Inc.Inventors: Fusen Chen, Frank R. Bryant, Girish Dixit
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Patent number: 5278098Abstract: A polycrystalline silicon layer is deposited and patterned to define a level of interconnect. Contact openings to lower conductive layers are then defined and patterned. A refractory metal such as tungsten is selectively deposited over the device, so that it adheres to the polycrystalline silicon in the interconnect leads and silicon of the lower conductive layer which is exposed in the contact openings. This provides a low resistance interconnect, and good, metal, contacts to underlying layers. Shared contacts between two or more polycrystalline silicon interconnect layers and in underlying conductive layers such as a substrate are easily formed using this technique.Type: GrantFiled: September 3, 1992Date of Patent: January 11, 1994Assignee: SGS-Thomson Microelectronics, Inc.Inventors: Che C. Wei, Chiara Zaccherini, Robert O. Miller, Girish A. Dixit
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Patent number: 5244827Abstract: A method for forming field oxide regions includes the formation of cavities in a semiconductor substrate. A layer of thermal oxide is then grown on the substrate. A layer of planarizing material is deposited over the device, filling the cavities. The planarizing layer is etched back to expose a portion of the cavities. A conformal layer of undoped oxide or a layer of polycrystalline silicon that is converted to oxide is deposited over the device, followed by a second layer of planarizing material, The planarizing material and conformal layer are then etched back to expose the active areas in the substrate.Type: GrantFiled: October 31, 1991Date of Patent: September 14, 1993Assignee: SGS-Thomson Microelectronics, Inc.Inventors: Girish A. Dixit, Fusen E. Chen, Robert O. Miller
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Patent number: 5233135Abstract: A technique for forming metal interconnect signal lines provides for planarization of an interlevel dielectric layer. A thin layer of material which can function as an etch stop, such as a metal oxide, is formed over the interlevel dielectric. An alignment process is used to pattern and define openings through the etch stop layer where contacts to underlying conductive regions will be formed. Another insulating layer is formed over the etch stop layer, and patterned to define all interconnect signal lines. When the signal line locations are etched away, the etching process stops on the etch stop layer in regions where the signal lines will be, and continues through to the underlying conductive layer where contacts are needed. A metal refill process can be used to then form interconnects and contacts within the etched holes, followed by an anisotropic etchback to remove any metal which lies on top of the upper insulating layer.Type: GrantFiled: June 28, 1991Date of Patent: August 3, 1993Assignee: SGS-Thomson Microelectronics, Inc.Inventors: Fusen E. Chen, Frank R. Bryant, Girish A. Dixit
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Patent number: 5182627Abstract: A method is provided for forming a polycrystalline silicon resistive load element of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A lightly doped first conductive layer having a conductivity of a first type. A first oxide layer is formed over the integrated circuit with a first opening therethrough exposing a portion of the first conductive layer. Using the first oxide layer as a mask, the exposed portion of the first conductive layer is then implanted with a dopant of a second conductivity type to form a junction between the exposed portion and the portion covered by the mask. A second oxide region is then formed on a portion of the first oxide layer in the first opening, over the junction and over a portion of the exposed first conductive layer adjacent to the junction. A silicide is formed over the exposed portion of the first conductive layer.Type: GrantFiled: September 30, 1991Date of Patent: January 26, 1993Assignee: SGS-Thomson Microelectronics, Inc.Inventors: Fusen E. Chen, Girish A. Dixit, Robert O. Miller
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Patent number: 5164340Abstract: The method for fabrication of openings in semiconductor devices to improve metal step coverage includes forming an active region over a substrate. A metal oxide layer is then formed over the source/drain region. An insulating layer is formed over the metal oxide layer. A photoresist layer is formed over the insulating layer, and patterned to form an opening, exposing a portion of the insulating. The insulating layer is then etched to expose a portion of the metal oxide layer. The photoresist layer is removed and the insulating layer is reflowed so as to form rounded corners at the opening of the insulating layer. The exposed portion of the metal oxide layer is removed to expose a portion of the active region.Type: GrantFiled: June 24, 1991Date of Patent: November 17, 1992Assignee: SGS-Thomson Microelectronics, IncInventors: Fusen Chen, Frank R. Bryant, Girish Dixit
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Patent number: 5108951Abstract: A method is provided for depositing aluminum thin film layers to form improved quality contacts in a semiconductor integrated circuit device. All or some of the deposition process occurs at relatively low deposition rates at a temperature which allows improved surface migration of the deposited aluminum atoms. Aluminum deposited under these conditions tends to fill contact vias without the formation of voids. The low temperature deposition step can be initiated by depositing aluminum while a wafer containing the integrated circuit device is being heated from cooler temperatures within the deposition chamber.Type: GrantFiled: November 5, 1990Date of Patent: April 28, 1992Assignee: SGS-Thomson Microelectronics, Inc.Inventors: Fusen E. Chen, Fu-Tai Liou, Yih-Shung Lin, Girish A. Dixit, Che-Chia Wei