Abstract: An apparatus and a method of depositing a catalytic layer comprising at least one metal selected from the group consisting of noble metals, semi-noble metals, alloys thereof, and combinations thereof in sub-micron features formed on a substrate. Examples of noble metals include palladium and platinum. Examples of semi-noble metals include cobalt, nickel, and tungsten. The catalytic layer may be deposited by electroless deposition, electroplating, or chemical vapor deposition. In one embodiment, the catalytic layer may be deposited in the feature to act as a barrier layer to a subsequently deposited conductive material. In another embodiment, the catalytic layer may be deposited over a barrier layer. In yet another embodiment, the catalytic layer may be deposited over a seed layer deposited over the barrier layer to act as a “patch” of any discontinuities in the seed layer. Once the catalytic layer has been deposited, a conductive material, such as copper, may be deposited over the catalytic layer.

Abstract: A method of measuring a concentration of conductive species in an aqueous system is disclosed. In one embodiment, the method comprises providing an electrochemical cell wherein the electrochemical cell has a cell resistance that varies with a concentration of conductive species and determining a relationship between the cell resistance of the electrochemical cell and the concentration of conductive species. The method further comprises measuring one or more electrochemical parameters of the electrochemical cell and determining a test concentration of conductive species based upon the one or more measured electrochemical parameters. Also disclosed is a system for electroplating a material layer on a substrate.

Abstract: The invention provides a removable first edge ring configured for pin and recess/slot coupling with a second edge ring disposed on the substrate support. In one embodiment, a first edge ring includes a plurality of pins, and a second edge ring includes one or more alignment recesses and one or more alignment slots for mating engagement with the pins. Each of the alignment recesses and alignment slots are at least as wide as the corresponding pins, and each of the alignment slots extends in the radial direction a length that is sufficient to compensate for the difference in thermal expansion between the first edge ring and the second edge ring.

Abstract: A structure and process is provided for filling integrated circuit cavities such as contacts and vias. These structures are filled at relatively low temperatures of no more than about 300° C., and preferably between about 20°-275° C., which temperature range permits for the use of low dielectric constant (&kgr;) polymers (i.e., &kgr;<˜3.0). Preferably, the cavities are provided with an elemental titanium-free liner to facilitate cavity filling, and the cavities are filled with CVD aluminum that is introduced into the cavities by way of a forcefill at pressures ranging from atmospheric to about 50 MPa, and preferably no more than about 30 MPa, at temperatures ranging from about 100°-300° C. Cavities filled in the foregoing manner exhibit electrical resistance levels that are up to 30% less than structures filled by conventional practices.

Abstract: A method and apparatus for plating substrates, wherein the apparatus includes a central substrate transfer enclosure having at least one substrate transfer robot positioned therein. A substrate activation chamber in communication with the central substrate transfer enclosure is provided and is accessible to the at least one substrate transfer robot. A substrate plating chamber in communication with the central substrate transfer enclosure is provided and is accessible to the at least one substrate transfer robot. A substrate spin rinse dry chamber in communication with the central substrate transfer enclosure is provided and is accessible to the at least one substrate transfer robot, and an annealing chamber in communication with the central substrate transfer enclosure is provided and is accessible to the at least one substrate transfer robot. At least one substrate pod loader in communication with the substrate transfer chamber and accessible to the at least one substrate transfer robot is also provided.

Abstract: An inter-level metallization structure and the method of forming it, preferably based on copper dual damascene in which the lower-metal level is formed with a exposed metallization and an adjacent, embedded stop layer, both the metallization and embedded stop layer have exposed surfaces approximately level with each other with a lower dielectric layer. The upper-metal level includes a second stop layer deposited over the embedded stop layer and the first metallization and a second dielectric layer. An inter-level via is etched through the second dielectric layer and through the second stop layer and metal is filled into the via to contact the metallization. If the inter-level via is offset over the edge of the metallization, the metal in the via contacts the embedded stop layer and not the first dielectric layer, whereby the embedded stop layer acts as a copper diffusion barrier.

Abstract: The present invention generally relates to an apparatus and method of evaluating electroplating solutions and conditions. In one embodiment, the method of evaluating electroplating solutions comprises utilizing an electrochemical measuring cell having a working electrode having a lid with at least one hole, a counter electrode, and a reference electrode. The working electrode, the counter electrode, and the reference electrode are immersed in at least one sample of at least one electroplating solution. The lid is disposed over the working electrode forming a chamber between the working electrode and the lid. The lid further has a hole to allow an electroplating solution to flow into the chamber and reach the working electrode. The potential of the working electrode in the sample of the electroplating solution is measured over time with a constant current supplied to the working electrode.

Abstract: A multi-step sputtering process in plasma sputter reactor having target and magnetron operable in two modes, for example, in a substrate sputter etch and a substrate sputter deposition. The target has an annular vault facing the wafer to be sputter coated. Various types of magnetic means positioned around the vault create a magnetic field supporting a plasma extending over a large volume of the vault. An integrated copper via filling process with the inventive reactor or other reactor includes a first step of highly ionized sputter deposition of copper, which can optionally be used to remove the barrier layer at the bottom of the via, a second step of more neutral, lower-energy sputter deposition of copper to complete the seed layer, and a third step of electroplating copper into the hole to complete the metallization. The first two steps can be also used with barrier metals.

Abstract: A target and magnetron for a plasma sputter reactor. The target has an annular vault facing the wafer to be sputter coated. Various types of magnetic means positioned around the vault create a magnetic field supporting a plasma extending over a large volume of the vault. An integrated copper via filling process includes a first step of highly ionized sputter deposition of copper, a second step of more neutral, lower-energy sputter deposition of copper to complete the seed layer, and electroplating copper into the hole to complete the metallization.

Abstract: A target and magnetron for a plasma sputter reactor. The target has an annular vault facing the wafer to be sputter coated. Various types of magnetic means positioned around the vault create a magnetic field supporting a plasma extending over a large volume of the vault. Preferably, the magnetron includes annular magnets of opposed polarities disposed behind the two vault sidewalls and a small closed unbalanced magnetron of nested magnets of opposed polarities scanned along the vault roof. An integrated copper via filling process with the inventive reactor or other reactor includes a first step of highly ionized sputter deposition of copper, which can optionally be used to remove the barrier layer at the bottom of the via, a second step of more neutral, lower-energy sputter deposition of copper to complete the seed layer, and a third step of electroplating copper into the hole to complete the metallization. The first two steps can be also used with barrier metals.

Abstract: Embodiments of the invention generally provide and apparatus and method for measuring organic additives in an ECP solution. The apparatus generally includes a high performance liquid chromatography (HPLC) column configured to receive an electrolyte fluid supply. The HPLC column operates to separate various organic additives from the electrolyte solution flowing therethrough. The remaining flow of electrolyte solution, which generally contains only a single organic additive therein, may then be passed to a CVS apparatus for analysis thereof. Inasmuch as the electrolyte flow contains only a single organic additive, the measurement accuracy is improved substantially. Further, a plurality of HPLC columns may be implemented to separate various organics out of the flowing electrolyte solution, and therefore, measure the flowing electrolyte solution for a plurality of organic additive concentrations therein.

Abstract: The present invention provides a composition and method for void-free plating of a metal into high aspect ratio features. The plating process is carried out in a plating solution containing metal at a molar concentration of between about 0.4 M and about 0.9 M, an acid at a concentration of between about 4 mg/L and about 40 mg/L, a suppressor at a concentration of between about 2 mL/L and about 15 mL/L, an accelerator at a concentration of between about 1.5 mL/L and about 8 mL/L, and a leveler at a concentration of between about 4 mL/L and about 11 mL/L.

Abstract: A method and associated apparatus of electroplating an object and filling small features. The method comprises immersing the plating surface into an electrolyte solution and mechanically enhancing the concentration of metal ions in the electrolyte solution in the features. In one embodiment, the mechanical enhancement comprises mechanically vibrating the plating surface. In another embodiment, the mechanical enhancement comprises mechanically vibrating the electrolyte solution. In a further embodiment, the mechanical enhancement comprises increasing the pressure applied to the electrolyte solution.

Abstract: A structure and process is provided for filling integrated circuit cavities such as contacts and vias. These structures are filled at relatively low temperatures of no more than about 300° C., and preferably between about 20°-275° C., which temperature range permits for the use of low dielectric constant (&kgr;) polymers (i.e., &kgr;<˜3.0). Preferably, the cavities are provided with an elemental titanium-free liner to facilitate cavity filling, and the cavities are filled with CVD aluminum that is introduced into the cavities by way of a forcefill at pressures ranging from atmospheric to about 50 MPa, and preferably no more than about 30 MPa, at temperatures ranging from about 100°- 300° C. Cavities filled in the foregoing manner exhibit electrical resistance levels that are up to 30% less than structures filled by conventional practices.

Abstract: A dual inlaid interconnect fabrication method using a temporary filler in a via during trench etch and removal of the filler after trench etch. This provides via bottom protection during trench etch.

Abstract: A metallization structure, and associated method, for filling contact and via apertures to significantly reduce the occurrence of microvoids and provide desirable grain orientation and texture. A modified barrier structure is set forth for contact apertures, and a modified liner structure is set forth for via apertures. The metallization fill structure for contact apertures includes a first wetting or glue layer of refractory metal on the contact aperture, a layer of TiN on the first wetting layer, a second wetting layer of plasma-treated refractory metal on the barrier layer, a layer of CVD Al on the second wetting refractory metal layer, and a PVD Al alloy to fill the contact aperture. The fill structure for via apertures includes an initial plasma-treated refractory metal liner deposited on the via aperture. A CVD Al liner is positioned on the initial refractory metal liner. A PVD Al alloy layer is positioned on the CVD Al liner to fill the via aperture.

Abstract: A method for forming a metal interconnect having a self-aligned transition metal-nitride barrier (124). After the metal interconnect lines (118) are formed, a transition metal (120) is deposited over the surface of the metal interconnect lines (118) and reacted in to form a metal-compound (122). The metal-compound (122) is then annealed in a nitrogen ambient to form a barrier layer (114) at the surface of the metal interconnect lines (118).

Abstract: A structure and process is provided for filling integrated circuit cavities such as contacts and vias. These structures are filled at relatively low temperatures of no more than about 300° C., and preferably between about 20°-275° C., which temperature range permits for the use of low dielectric constant (&kgr;) polymers (i.e., &kgr;<˜3.0). Preferably, the cavities are provided with an elemental titanium-free liner to facilitate cavity filling, and the cavities are filled with CVD aluminum that is introduced into the cavities by way of a forcefill at pressures ranging from atmospheric to about 50 M Pa, and preferably no more than about 30 M Pa, at temperatures ranging from about 100°-300° C. Cavities filled in the foregoing manner exhibit electrical resistance levels that are up to 30% less than structures filled by conventional practices.

Abstract: A target and magnetron for a plasma sputter reactor. The target has an annular vault facing the wafer to be sputter coated. Various types of magnetic means positioned around the vault create a magnetic field supporting a plasma extending over a large volume of the vault. An integrated copper via filling process includes a first step of highly ionized sputter deposition of copper, a second step of more neutral, lower-energy sputter deposition of copper to complete the seed layer, and electroplating copper into the hole to complete the metallization.

Abstract: A method for selectively coupling a conductive material (60) to a contact region (32) of a semiconductor device (8) includes bombarding residual material (40) coupled to the contact region (32) with inert ions (44) at a first position associated with an integrated cluster tool (90) to increase the reactive surface area of the residual material (40). Hydrogen ions (46) are introduced at the first position for reaction with the residual material (40) to remove the residual material (40) from the contact region (32). The semiconductor device (8) is transferred in situ from the first position to a second position associated with the integrated cluster tool (90). The conductive material (60) is selectively coupled to the contact region (32) at the second position using chemical vapor deposition.