Abstract: Methods, systems, and devices for dynamic status registers array are described. An apparatus may include one or more memory dice coupled with a data bus. The apparatus may further include a controller coupled with each of the memory dice via the data bus that is configured to transmit a first command associated with a first operation to a first memory die. The first command may assign an associated operation (e.g., the first operation) to a queue slot of a status bank that is associated with at least the first memory die. The controller may further transmit second command to the first memory die to request a status of the first operation. The controller may receive a status of the first operation via a channel (e.g., a first channel) of the data bus that is based on the assigned queue slot of the status bank.

Abstract: Systems and methods are disclosed comprising receiving a request for a descriptor of a storage system, sending the descriptor to the host including an indication that a component of the storage device is in a restricted operation mode, wherein the host device utilizes the indication to determine a boot mode of the host device.

Abstract: Methods, systems, and devices for atomic write operations are described. A host system may receive a sequence of data that includes a first set of data and a second set of data. The host system may determine, based on the sequence of data, a first set of contiguous logical addresses for the first set of data and a second set of contiguous logical address for the second set of data. The host system may then transmit to a memory system a write command that indicates the first set of contiguous logical addresses and the second set of contiguous logical addresses. The first set of contiguous logical addresses may be discontiguous with the second set of contiguous logical addresses.

Abstract: Methods, systems, and devices for usage level identification for memory device addresses are described. Systems, techniques, and devices are described herein in which a memory device may determine where to store data according to a level of usage of the data. The memory device may receive a write command indicating data to be written, a type of the data, and a logical address of a memory array for writing the data. The memory device may identify an entry associated with the logical address in a table that maps the logical address to a physical address of the memory array. The entry may include a field configured to maintain a level of usage for the logical address. The memory device may update the level of usage value according to a process and write the data to a physical address of the memory array based on the level of usage value.

Abstract: Methods, systems, and devices for suspending operations of a memory system are described. A memory system may be configured to perform a write operation to store data in a nonvolatile memory device, where the write operation includes storing information in one or more latches associated with the nonvolatile memory device; receive a suspend command to suspend performance of the write operation based on a request to perform a read operation associated with a higher-priority than the write operation; suspend the performance of the write operation based on receiving the suspend command; transmit the information stored in the one or more latches associated with the nonvolatile memory device to a host system based on suspending the performance of the write operation; and perform the read operation based at least in part on transmitting the information to the host system.

Abstract: Methods, systems, and devices for configurable types of write operations are described. A memory device may receive a write command to write data in a zone of a memory system. The memory device may identify a physical address to store the data using a cursor associated with the zone based at least in part on receiving the write command. In some examples, the cursor may be associated with a type of a write operation based on a quantity of data associated with the cursor. As such, the memory device write, using a first type of the write operation or a second type of the write operation in accordance with the quantity of data, the data, and an indication of the type of the write operation used to write the data into the memory system.

Abstract: Methods, systems, and devices for compression and decompression of trim data are described. A memory system may store one or more trim settings to a volatile memory in a compressed manner, and may expand (e.g., decompress) the data as part of a write operation to a non-volatile memory (e.g., during a start-up procedure). For example, compressed (e.g., non-expanded) data including trim settings may be stored to a volatile memory, and a portion of the array of volatile memory cells may be temporarily allocated to expand the data (e.g., copy the data, invert the data, copy the inverted data). Once the data is expanded, it may be stored in the non-volatile memory, and the temporarily allocated portion of the array of volatile memory cells may be reallocated (e.g., allocated for another purpose). The expanded data may include multiple copies and inverted copies of the trim settings.

Abstract: Methods, systems, and devices for improving write quality in memory systems are described. The memory system may receive, from a host system, a command to perform an operation. The memory system may determine an availability parameter that indicates processing resources of the memory system that are available to perform the operation based on receiving the command. In some cases, the memory system may transmit, to the host system, a message comprising the availability parameter, and the host system may delay transmission of one or more pending commands based on receiving the message comprising the availability parameter.

Abstract: Methods, systems, and devices for determining locations in memory for boot-up code are described. An indication of one or more timeout durations for a boot sequence is received. Information for the boot sequence is stored in one or more memory cells based on the one or more timeout durations, where the one or more memory cells is selected based on a read latency, an error rate, or a storage-level of the one or more memory cells with relation to the indicated one or more timeout durations. The information for the boot sequence stored in the one or more memory cells is accessed based on an initialization of the boot sequence.

Abstract: Methods, systems, and devices for weighted valid address count (VAC) for garbage collection are described. A memory system may select a data block for reorganization (e.g., garbage collection) based on a weighted VAC. The memory system may include valid data units associated with various types of data and may track respective quantities of valid data units associated with respective types of data. The memory system may determine the weighted VAC of the data block based on a weighted average of the respective quantities of valid data units, where respective weights may be applied to the respective quantities of valid data units. The memory system may select the data block based on the weighted VAC, which may be different than a total VAC of the data block, and may perform a reorganization procedure on the selected data block.

Abstract: Methods, systems, and devices for low-power boot-up for memory systems are described. A memory system may be configured to receive, over a first conductive path of a second communication interface, a first indication to boot-up a memory system and a first communication interface associated with the memory system, wherein the first communication interface includes a plurality of conductive paths; receive, over a second conductive path of the second communication interface, a second indication whether to perform a boot-up operation of the memory system using a low-power mode or a high-power mode based at least in part on receiving the first indication; and boot the memory system according to the low-power mode or the high-power mode based at least in part on receiving the second indication.

Abstract: Methods, systems, and devices for dual address encoding for logical-to-physical mapping are described. A memory device may identify a first physical address corresponding to a first logical block address generated by a host device and a second physical address corresponding to a second (consecutive) logical block address generated by a host device. The memory device may store the first physical address and second physical address in a single entry of a logical-to-physical mapping table that corresponds to the first logical block address. The memory device may transmit the logical-to-physical table to the host device for storage at the host device. The host device may subsequently transmit a single read command to the memory device that includes the first physical address and the second physical address based on the logical-to-physical table.

Abstract: Methods, systems, and devices for suspend operations are described. A memory device may perform a write operation including one or more programming phases and one or more verify phases. The memory device may receive a read command while performing the write operation and determine whether the verify phase of the write operation is complete. The memory device may suspend a performance of the write operation in response to determining that the verify phase of the write operation is complete. The memory device may transmit first information for the write operation from a first latch to a volatile memory device in response to suspending the performance of the write operation. The memory device may perform a read operation associated with the read command in response to suspending the performance of the write operation and transferring the first information.

Abstract: Methods, systems, and devices for configurable verify level are described. A host device may determine a target level of reliability for a set of data stored in a memory device. The host device may transmit, to the memory device, a command indicating the target level of reliability and a request to perform one or more error management operations for the set of data based on or in response to the target level of reliability. The memory device may determine the target level of reliability and the corresponding error management operations based on or in response to the command. The memory device may perform the error management operations for the set of data. The memory device may transmit, to the host device, an indication of a level of reliability of the set of data based on or in response to the command and performing the set of error management operations.

Abstract: Methods, systems, and devices for memory operations are described. Data for a set of commands associated with a barrier command may be written to a buffer. Based on a portion of the data to be flushed from the buffer, a determination may be made as to whether to update an indication of a last barrier command for which all of the associated data has been written to a memory device. Based on whether the indication of the last barrier command is updated, a flushing operation may be performed that transfers the portion of the data from the buffer to a memory device. During a recovery operation, the portion of the data stored in the memory device may be validated based on determining that the barrier command is associated with the portion of the data and on updating the indication of the last barrier command to indicate the barrier command.

Abstract: Methods, systems, and devices for determining locations in memory for boot-up code are described. An indication of one or more timeout durations for a boot sequence is received. Information for the boot sequence is stored in one or more memory cells based on the one or more timeout durations, where the one or more memory cells is selected based on a read latency, an error rate, or a storage-level of the one or more memory cells with relation to the indicated one or more timeout durations. The information for the boot sequence stored in the one or more memory cells is accessed based on an initialization of the boot sequence.

Abstract: Methods, systems, and devices for signaling memory zone ranking information are described. A first system may determine ranking information for zones of a memory. The ranking information may be associated with a first type of maintenance operation. The first system may transmit the ranking information to a second system. The second system may use the ranking information to manage a second type of maintenance operation.

Abstract: Apparatus and methods are disclosed, including receiving an indication to selectively erase first data stored on a first page of a first subset of a group of multi-level memory cells of the storage system, each multi-level memory cell comprising multiple pages and providing, in response the indication to selectively erase the first data, at least one soft erase pulse to the first page of memory cells associated with the first data to induce distribution overlap across different bit levels of the first page of the group of multi-level memory cell.

Abstract: Methods, systems, and devices for techniques for sequential access operations are described. In some cases, a memory system may be configured to suppress storing a checkpoint while in a sequential write mode. While in the sequential write mode, the memory system may initiate and store a first a checkpoint, along with an indication that the checkpoint was stored as part of the sequential write mode. Subsequently, the memory system may initiate a second checkpoint and suppress storing the second checkpoint. In some cases, to rebuild an address mapping after an asynchronous power loss, the memory system may access a last stored checkpoint to determine whether the checkpoint was stored as part of a sequential write mode. The memory system may generate logical addresses for data stored after the last checkpoint and before the asynchronous power loss using a starting logical address, as well as an ending logical address.

Abstract: Methods, systems, and devices for techniques for memory system rebuild are described. In some cases, a memory system may store an indication of whether data stored to one or more physical addresses is sequential using metadata associated with the one or more physical addresses. For metadata corresponding to a beginning physical address, the memory system may store an indication of a quantity of physical addresses subsequent to the beginning physical address with sequential corresponding logical addresses. Additionally or alternatively, the memory system may store an indication of a quantity of physical addresses preceding a last physical address with sequential corresponding logical addresses. During a rebuild operation, the memory system may read the stored indication and may rebuild an address mapping algorithmically using the stored indication.