Abstract: Methods, systems, and devices for current budget adaption are described. A controller may be coupled with a set of memory devices. The controller may receive current consumption information from the set of memory devices and update a current consumption budget for the set of memory devices based on the current consumption information.

Abstract: Methods, systems, and devices for overwriting at a memory system are described. A memory system may be configured to overwrite portions of a memory array with new data, which may be associated with omitting an erase operation. For example, write operations may be performed in accordance with a first demarcation configuration to store information at a portion of a memory array. A portion of a memory system may then determine to overwrite the portion of the memory array with different or updated information, which may include performing write operations in accordance with a second demarcation configuration. The second demarcation configuration may be associated with different cell characteristics for a one or more logic states, such as different distributions of stored charge or other cell property, different demarcation characteristics, different write operations, among other differences, which may support performing an overwrite operation without first performing an erase operation.

Abstract: Methods, systems, and devices for configurable verify level are described. A host device may determine a target level of reliability for a set of data stored in a memory device. The host device may transmit, to the memory device, a command indicating the target level of reliability and a request to perform one or more error management operations for the set of data based on or in response to the target level of reliability. The memory device may determine the target level of reliability and the corresponding error management operations based on or in response to the command. The memory device may perform the error management operations for the set of data. The memory device may transmit, to the host device, an indication of a level of reliability of the set of data based on or in response to the command and performing the set of error management operations.

Abstract: Methods, systems, and devices for dynamic status registers array are described. An apparatus may include one or more memory dice coupled with a data bus. The apparatus may further include a controller coupled with each of the memory dice via the data bus that is configured to transmit a first command associated with a first operation to a first memory die. The first command may assign an associated operation (e.g., the first operation) to a queue slot of a status bank that is associated with at least the first memory die. The controller may further transmit second command to the first memory die to request a status of the first operation. The controller may receive a status of the first operation via a channel (e.g., a first channel) of the data bus that is based on the assigned queue slot of the status bank.

Abstract: Methods, systems, and devices for using a completion flag for memory operations are described. A completion flag for a memory device may indicate whether at least one access operation has been completed at the memory device. A controller may poll the completion flag, and if the completion flag indicates that at least one access operation has been completed at the memory device, the controller may poll a status register for the memory device to obtain additional information regarding one or more completed access operations at the memory device.

Abstract: Methods, systems, and devices for logic remapping techniques are described. A memory system may receive a write command to store information at a first logical address of the memory system. The memory system may generate a first entry of a logical-to-physical mapping that maps the first logical address with a first physical address that stores the information. The memory system may perform a defragmentation operation or other remapping operation. In such a defragmentation operation, the memory system may remap the first logical address to a second logical address, such that the second logical address is mapped to the first physical address. The memory system may generate a second entry of a logical-to-logical mapping that maps the first logical address with the second logical address.

Abstract: Methods, systems, and devices for read latency and suspend modes are described. A memory system may operate in a first mode of operation associated with a first set of access operations including executing read operations, executing write operations, and suspending write operations. The memory system may receive, from a host system, an indication to switch to a second mode of operation associated with a decreased latency for executing write operations based on limiting a suspension of write operations. For example, the host system may transmit a command including the indication to switch to the second mode of operation. In another example, the host system may write a value to a register at the memory system including the indication to switch to the second mode of operation. Based on receiving the indication from the host system, the memory system may then operate according to the second mode of operation.

Abstract: A variety of applications can include memory systems that have one or more memory devices capable of performing memory operations on multiple blocks of memory in response to a command from a host. For example, improvement in erase performance can be attained by erasing multiple blocks of memory by one of a number of approaches. Such approaches can include parallel erasure followed by serial verification in response to a single command. Other approaches can include sequential erase and verify operations of the multiple blocks in response to a single command. Additional apparatus, systems, and methods are disclosed.

Abstract: The disclosure describes a programmable power management system for NAND Flash devices. In one embodiment, dedicated match logic is provided to store program counters responsible for peak power consumption of one or more NAND Flash dies. Upon detecting that a current program counter equals a stored program counter, a high current enable signal is toggled causing at least one NAND Flash die to suspend operations, thereby reducing peak power consumption of the NAND Flash device.

Abstract: Methods, systems, and devices for reduced pin status register are described. An apparatus may include a first memory die and a second memory die each coupled with a data bus. The apparatus may further include a controller coupled with the first memory die and the second memory die via the data bus that is configured to transmit a first command associated with a first operation to the first memory die and a second command associated with a second operation to the second memory die. The controller may further transmit a third command concurrently to the first memory die and the second memory die, the third command requesting a first status of the first operation and a second status of the second operation. The controller may receive the first status and the second status concurrently via the data bus from the first memory die and the second memory die.

Abstract: Methods, systems, techniques, and devices for smart factory reset procedures are described. In accordance with examples as disclosed herein, a memory system may receive one or more commands associated with a reset procedure. The memory system may identify, in response to the one or more commands, a first portion of one or more memory arrays of the memory system as storing user data and a second portion of the one or more memory arrays as storing data associated with an operating system. The memory system may update a mapping of the memory system based on identifying the first portion and the second portion. The memory system may transfer the data associated with the operating system to a third portion of the one or more memory arrays and perform an erase operation on a subset of physical addresses of the set of physical addresses.

Abstract: Devices and techniques for adjustable memory device write performance are described herein. An accelerated write request can be received at a memory device from a controller of the memory device. The memory device can identify that a target block for external writes is opened as a multi-level cell block. The memory device can then write data for the accelerated write request to the target block using a single-level cell encoding.

Abstract: Methods, systems, and devices for compressed logical-to-physical mapping for sequentially stored data are described. A memory device may use a hierarchical set of logical-to-physical mapping tables for mapping logical block address generated by a host device to physical addresses of the memory device. The memory device may determine whether all of the entries of a terminal logical-to-physical mapping table are consecutive physical addresses. In response to determining that all of the entries contain consecutive physical addresses, the memory device may store a starting physical address of the consecutive physical addresses as an entry in a higher-level table along with a flag indicating that the entry points directly to data in the memory device rather than pointing to a terminal logical-to-physical mapping table. The memory device may, for subsequent reads of data stored in one or more of the consecutive physical addresses, bypass the terminal table to read the data.

Abstract: Methods, systems, and devices for recovery of logical-to-physical (L2P) table information for a memory device are described. A memory system may detect an error in one or more pointers of the L2P table using an error detecting code that is uncorrectable using the code. The memory system may determine a set of candidate codewords for the set of bits, where each of the candidate codewords includes one or more corresponding candidate pointers, and check whether a candidate codeword is correct based on whether a logical address corresponding to a candidate pointer of the candidate codeword matches a logical address stored as metadata for a set of data at a physical address pointed to by the candidate pointer. The memory system may limit the set of candidate codewords or order the candidate codewords for evaluate to reduce a latency associated with identifying a correct candidate codeword.

Abstract: Systems and methods of memory operation involving dynamic adjustment of write policy based on performance needs are disclosed. In one embodiment, an exemplary method may comprise monitoring memory performance parameters related to a programming operation being scheduled, selecting a write policy based on the memory performance parameters monitored, executing a memory control process that is configured to switch between the first addressing scheme and the second addressing scheme, and programming a first superpage of the programming operation using the first addressing scheme and programing a second superpage of the programming operation using the second addressing scheme.

Abstract: Devices and techniques are disclosed herein for providing L2P information to a host device from a storage system, the L2P information comprising changed L2P region and associated subregion information, to-be-loaded L2P region and associated subregion information, and invalid L2P region and associated subregion information.

Abstract: Methods, systems, and devices for techniques for failure management in memory systems are described. A memory system may include one or more non-volatile memory devices. A set of physical blocks of memory cells of the one or more non-volatile memory devices may be grouped into virtual blocks, where each physical block of a virtual may block may be within a different plane of the one or more non-volatile memory devices. The memory system may detect a failure within a physical block of a virtual block and may transfer data from the physical block to one or more other physical blocks within the same virtual block in response to detecting the failure.

Abstract: Methods, systems, and devices for page validity table colors for garbage collection are described. The memory system may obtain validity information and information associated with a characteristic for each page of a block of data and based on initiating a reorganization procedure on the block of data of the memory system. The memory system may move, for the reorganization procedure, a first set of pages of the block of data associated with a first value of the characteristic to a first portion of the memory system according to the validity information for the first set of pages. The memory system may move, for the reorganization procedure, a second set of pages of the block of data associated with a second value of the characteristic to a second portion of the memory system according to the validity information for the second set of pages.

Abstract: Methods, systems, and devices for dynamic superblocks are described. In some examples, a superblock may be established across one or more dice of a memory device. A superblock may include one or more blocks from a plurality of planes of a memory die, and may be associated with a first performance cursor or a second performance cursor. The superblock may be established based on one or more criteria, such as a quantity of available blocks in a plane, a quantity of access operations performed on one or more blocks in a plane, or other criteria. Establishing a superblock associated with a first performance cursor may allow for performance criteria established by a host device to be maintained, while establishing a superblock associated with a second performance cursor may allow for garbage collection, wear leveling, and other maintenance operations to be performed on the memory device.

Abstract: Methods, systems, and devices for secure self-purging memory partitions are described. Systems, techniques and devices are described herein in which data stored in a portion of a secure partition of memory may be removed from the secure partition. In some examples, a portion of secure partition may be allocated as self-purging memory such that data stored therein may be selectively removed in response to a logic address associated with the data being overwritten. In some cases, the data may be removed by programming the memory cells associated with the data to a specific voltage distribution. In some cases, the secure partition may include separate portions having different sets of operating parameters for access operations.