Abstract: An apparatus and method for forming optical black pixels having uniformly low dark current. Optical Black opacity is increased without having to increase Ti/TiN layer thickness. A hybrid approach is utilized combining a Ti/TiN OB layer in conjunction with in-pixel metal stubs that further occlude the focal radius of each pixel's incoming light beam. Additional metal layers can be used to increase the opacity into the infrared region.

Abstract: Systems and methods are provided that facilitate employing a plurality of independent reset buses for a column of pixels in a pixel array of a CMOS sensor imager. Utilization of the plurality of independent reset buses for the column of pixels can enable independent reset to be effectuated when employing sub-frame integration. For example, rows to be read and reset during a given readout time interval can be selected based upon one or more criteria. Further, each of the rows selected during the given readout time interval can be associated with a respective distinct reset bus. By leveraging the plurality of independent reset buses, uniformity in pixel operation can be maintained whether operating in full frame integration mode or sub-frame integration mode. Thus, noise resultant from changing between integration modes can be mitigated by using the plurality of independent reset buses.

Abstract: An CMOS active pixel sensor (APS) imaging system include circuitry to compensate for different analog offset levels from the CMOS pixel array. More specifically, the compensation is performed in the analog (charge) domain. A digital correction value, which may be measured as part of the operation or testing of the CMOS APS system, is provided to a offset correction block circuit, to generate an analog electrical signal. The analog electrical signal is supplied to a sample-and-hold circuit including a charge amplifier. The signal read from the pixel array, after conditioning through an analog signal chain, is also supplied to the charge amplifier, which has a linear transfer function and outputs the compensated signal.

Abstract: A high dynamic range amplifier circuit for amplifying pixel signals of an imager device is disclosed. The amplifier circuit uses a read-out scheme based on a charge recycling approach, where a pixel signal is first amplified with a low gain during a first amplification phase T1, and then the amplifier output is immediately recycled and the pixel signal amplified with a higher gain during a second amplification phase T2.

Abstract: An image sensor, system and method that alternates sub-sets of pixels with long exposure times and pixels with short exposure times on the same sensor to provide a sensor having improved Wide Dynamic Range (WDR). The sub-sets of pixels are reset at different time intervals after being read, which causes the respective integration times to vary. By combining information contained in the both the short and long integration pixels, the dynamic range of the sensor is improved.

Abstract: An analog signal chain for a CMOS active pixel sensor imaging system utilizes, for each amplification stage, a plurality of fixed gain amplifiers instead of a single multi-gain amplifier. The fixed gain amplifier corresponding to the desired gain level is selected and powered on and coupled to the input/output signal paths, while the non-selected fixed gain amplifier(s) are powered off and isolated from the input/output signal paths. Each fixed gain amplifier is operated at a gain bandwidth corresponding to the timing requirements of the imaging system and the gain of the amplifier. Thus, each fixed gain amplifier (other than the one corresponding to the maximum gain of a comparable multi-gain amplifier) operates at a lower level of power consumption than the comparable multi-gain amplifier.

Abstract: The claimed subject matter provides systems and/or methods that facilitate generating and/or maintaining low noise reference voltages for CMOS imaging System-on-Chip (iSoC) sensors. A primary reference voltage can be generated utilizing a low noise bandgap. Further, the primary reference voltage can be filtered via a low pass filter. The filtered, primary reference voltage can thereafter be distributed to a plurality of isolated domains. Each of the isolated domains can generate an independent set of reference voltages based upon the filtered, primary reference voltage. Moreover, subsets of these reference voltages can be employed by programmable digital to analog converters (DACs). Each of the reference voltages can be isolated from switching noise and/or clock glitches generated within each domain. Further, each DAC output can be buffered to have adequately low impedance with appropriate drive capability and requisite signal swing.

Abstract: An analog signal chain for a CMOS active pixel sensor imaging system utilizes, for each amplification stage, a plurality of fixed gain amplifiers instead of a single multi-gain amplifier. The fixed gain amplifier corresponding to the desired gain level is selected and powered on and coupled to the input/output signal paths, while the non-selected fixed gain amplifier(s) are powered off and isolated from the input/output signal paths. Each fixed gain amplifier is operated at a gain bandwidth corresponding to the timing requirements of the imaging system and the gain of the amplifier. Thus, each fixed gain amplifier (other than the one corresponding to the maximum gain of a comparable multi-gain amplifier) operates at a lower level of power consumption than the comparable multi-gain amplifier.

Abstract: An imager temperature sensor and a current correction apparatus are provided which use dark pixel measurements from an imager chip during operation together with a fabrication process constant as well as a chip dependent constant to calculate chip temperature. The chip temperature may be used to generate a current correction signal. The correction signal is used to tune a current on the imager chip to correct for temperature variations.

Abstract: A black clamp stabilization circuit for an image sensor utilizes a mixed-signal SoC block comprising sub-blocks to dynamically and precisely adjust the black level based on comparison to a reference black level. The black level adjustments include a first level regulation using digital control of an analog signal in a feedback loop that includes a programmable gain amplifier and high-resolution A/D converter. By applying the black clamping in the analog domain, dynamic range is extended. Additional black level regulation is subsequently performed in the digital domain to differentially eliminate line noise and column noise generated within the imaging System-on-Chip. By providing information between the sub-blocks, the algorithms can converge more quickly. The technique enables multiple signal paths to separately handle individual colors and to increase imaging data throughput.

Abstract: A method and apparatus for minimizing noise pickup in iSoC sensors using an improved Analog Capacitor Memory (ACM) design and optimized timing methods that together prevent direct connection of the electrical grounds between the low-speed signal processing circuit and high-speed signal processing circuit of an imaging System-on-Chip sensor. The ACM includes a two-terminal capacitor and two pairs of terminals. Each pair of terminals is connected via switches to separate circuits. The switches are controlled to isolate one side of the ACM from the other, thereby reducing the noise pickup between the circuits.

Abstract: A method and apparatus for forming dummy pixels exhibiting electrical characteristics virtually identical to the clear pixels of the imaging array. Arrays of such dummy pixels are used to form regions that isolate the main imaging array and sub-arrays of optical black pixels while preventing edge effects. The dummy pixels are preferably clear but can also be covered with optical black. By setting quiescent operation in soft reset, the dummy pixels exhibit the diode ideality and RoA product that are typical of any of the pixels in the entire array.

Abstract: A voltage amplifier is provided. The voltage amplifier includes an amplifier stage to amplify an input signal. A bias current generator supplies a bias current to the amplifier stage. The bias current generator is controllable in response to a frame rate signal that is representative of a video frame rate. A compensation network stabilizes a loop response of the voltage amplifier. The compensation network is controllable in response to the frame rate signal.

Abstract: Systems and methods are provided that facilitate staggering resets of rows of pixels in a CMOS imaging iSoC sensor. Reset signals and select signals can be provided to pixels in a pixel array in a coordinated manner when employing full frame integration or sub-frame integration. Further, reset signals and select signals can be transferred to a first row of pixels, while reset signals can be transferred to a second row of pixels during a unique readout time interval when utilizing sub-frame integration. Within the unique readout time interval, reset signals can be transferred to the first row of pixels during a first time period, while reset signals can be transferred to the second row of pixels during a second time period, where the first and second time periods are non-overlapping. Accordingly, cross-talk between rows of pixels during reset can be mitigated, which leads to enhanced uniformity.

Abstract: An image sensor, in which, a planarized layer is formed on a semiconductor substrate including a pixel array region, an optical black region, and a logic region to cover a photo sensing unit array in the pixel array region, a patterned metal layer is formed on the planarized layer corresponding to the pixel array region and the logic region, but not the optical black region. An optical black layer is formed in the optical black region after a passivation layer is formed and before a color filter array is formed at a temperature less than about 400° C., and preferably contains metal material.

Abstract: A new capacitor architecture includes a front plate of the capacitor formed from a first polysilicon layer. The front plate is surrounded by a first dielectric layer and a second dielectric layer. The back plate of the capacitor is formed from one layer of a first two-layer conductive structure which surrounds the first dielectric layer and the second dielectric layer. The two-layer conductive structure is an equal potential structure and includes a conductive coupling between the two layers.

Abstract: Signals from an imager pixel photodetector are received by an amplifier having capacitive feedback, such as a capacitive transimpedance amplifier (CTIA). The amplifier can be operated at a low or no power level during an integration period of a photodetector to reduce power dissipation. The amplifier can be distributed, with an amplifier element within each pixel of an array and with amplifier output circuitry outside the pixel array. The amplifier can be a single ended cascode amplifier, a folded cascode amplifier, a differential input telescopic cascode amplifier, or other configuration. The amplifier can be used in pixel configurations where the amplifier is directly connected to the photodetector, or in configurations which use a transfer transistor to couple signal charges to a floating diffusion node with the amplifier being coupled to the floating diffusion node.

Abstract: An apparatus such as an imager includes groups of sensors each of which includes subgroups of sensors. Subgroup select circuits are coupled to outputs from respective subgroups of sensors, and group select circuits are coupled to outputs from subgroup select circuits associated with respective ones of the groups. A bus is coupled to receive outputs from the group select circuits. A controller can provide control signals to the subgroup select circuits and the group select circuits to selectively enable the respective subgroup select circuits and group select circuits to pass signals from the sensors to the bus one sensor at a time.

Abstract: Circuits, methods, and systems are disclosed in which a current is provided to compensate for spurious current while receiving signals through a line. For example, the spurious current can be sensed and the compensating current can be approximately equal to the sensed spurious current. The spurious current could include photocurrent from a bright light, and the compensating current can prevent bright light effects.

Abstract: An analog differential voltage circuit is disclosed that enables the combination of a plurality of voltage signals in the analog domain of a CMOS processing system prior to being received by a differential amplifier and prior to being digitized. By programming the column decoder to read out a plurality of column buffer circuits, a plurality of linear operations (e.g., addition, substation, averaging, weighted, sum) may be performed on the plurality of analog voltage levels prior to their being digitized.