Abstract: An imager temperature sensor and a current correction apparatus are provided which use dark pixel measurements from an imager chip during operation together with a fabrication process constant as well as a chip dependent constant to calculate chip temperature. The chip temperature may be used to generate a current correction signal. The correction signal is used to tune a current on the imager chip to correct for temperature variations.

Abstract: An analog to digital conversion (ADC) circuit is disclosed including a fully differential reference voltage source. The reference voltage source includes a programmable current supply adapted to drive a programmed current through a resistor so as to establish an initial reference voltage. The initial reference voltage is sampled onto a capacitive network during a first sampling time interval. The capacitive network is coupled to a differential input of a fully differential amplifier, and maintained at a differential output of the differential amplifier during a second output time interval. An output coupling between the differential output and differential input of the differential amplifier acts to maintain stability of the output voltage during the output time interval.

Abstract: A new capacitor architecture includes a front plate of the capacitor formed form a first polysilicon layer. The front plate is surround by first and second dielectric layers. The back plate of the capacitor is formed from one layer of a first two-layer conductive structure which surrounds the first and second dielectric layer. The two layer structure is an equal potential structure and includes a conductive coupling between the two layers. In one embodiment, the back plate of the capacitor is formed from a metal layer. A third and fourth dielectric layers surround the first two-layer conductive structure. A second two-layer equal potential conductive structure surrounds the third and fourth dielectric layers. In one embodiment, the second two-layer equal potential conductive structure comprise an interconnect between a metal layer and the substrate.

Abstract: An analog to digital conversion (ADC) circuit is disclosed including a fully differential reference voltage source. The reference voltage source includes a programmable current supply adapted to drive a programmed current through a resistor so as to establish an initial reference voltage. The initial reference voltage is sampled onto a capacitive network during a first sampling time interval. The capacitive network is coupled to a differential input of a fully differential amplifier, and maintained at a differential output of the differential amplifier during a second output time interval. An output coupling between the differential output and differential input of the differential amplifier acts to maintain stability of the output voltage during the output time interval.

Abstract: An imager temperature sensor and a current correction apparatus are provided which use dark pixel measurements from an imager chip during operation together with a fabrication process constant as well as a chip dependent constant to calculate chip temperature. The chip temperature may be used to generate a current correction signal. The correction signal is used to tune a current on the imager chip to correct for temperature variations.

Abstract: Circuits, methods, and systems are disclosed in which a current is provided to compensate for spurious current while receiving signals through a line. For example, the spurious current can be sensed and the compensating current can be approximately equal to the sensed spurious current. The spurious current could include photocurrent from a bright light, and the compensating current can prevent bright light effects.

Abstract: Preferred embodiments include receiving input defining dimensions for a workcell and a size and location for one or more objects within the workcell, receiving input defining a walking velocity for an operator within the workcell and one or more tasks to be completed during a workcell cycle, receiving input defining one or more times and locations to complete the one or more tasks within the workcell, calculating a total walking time to complete the one or more tasks during the workcell cycle based upon the size and location of the object(s), the time(s) and location(s) to complete the task(s) and the operator walking velocity, and outputting the total walking time for the workcell cycle and a graphical representation of the workcell including the object(s) and an operator walking path between points within the workcell at which the one or more tasks are completed.

Abstract: A high dynamic range amplifier circuit for amplifying pixel signals of an imager device is disclosed. The amplifier circuit uses a read-out scheme based on a charge recycling approach, where a pixel signal is first amplified with a low gain during a first amplification phase T1, and then the amplifier output is immediately recycled and the pixel signal amplified with a higher gain during a second amplification phase T2.

Abstract: A CMOS imager has a programmable current multiplication stage provided between a master current reference and the analog circuitry. The master current of each chip can be stored on-chip, for example, in a fuse-type ROM during production testing. By programming the current multiplication stage using the stored master current information, the master current can be chosen correctly for each chip, regardless of variations in manufacturing, thereby improving the production specification to the customer.

Abstract: An analog to digital conversion (ADC) circuit is disclosed including a fully differential reference voltage source. The reference voltage source includes a programmable current supply adapted to drive a programmed current through a resistor so as to establish an initial reference voltage. The initial reference voltage is sampled onto a capacitive network during a first sampling time interval. The capacitive network is coupled to a differential input of a fully differential amplifier, and maintained at a differential output of the differential amplifier during a second output time interval. An output coupling between the differential output and differential input of the differential amplifier acts to maintain stability of the output voltage during the output time interval.

Abstract: A high dynamic range amplifier circuit for amplifying pixel signals of an imager device is disclosed. The amplifier circuit uses a read-out scheme based on a charge recycling approach, where a pixel signal is first amplified with a low gain during a first amplification phase T1, and then the amplifier output is immediately recycled and the pixel signal amplified with a higher gain during a second amplification phase T2.

Abstract: An CMOS active pixel sensor (APS) imaging system include circuitry to compensate for different analog offset levels from the CMOS pixel array. More specifically, the compensation is performed in the analog (charge) domain. A digital correction value, which may be measured as part of the operation or testing of the CMOS APS system, is provided to a offset correction block circuit, to generate an analog electrical signal. The analog electrical signal is supplied to a sample-and-hold circuit including a charge amplifier. The signal read from the pixel array, after conditioning through an analog signal chain, is also supplied to the charge amplifier, which has a linear transfer function and outputs the compensated signal.

Abstract: A new capacitor architecture includes a front plate of the capacitor formed form a first polysilicon layer. The front plate is surround by first and second dielectric layers. The back plate of the capacitor is formed from one layer of a first two-layer conductive structure which surrounds the first and second dielectric layer. The two layer structure is an equal potential structure and includes a conductive coupling between the two layers. In one embodiment, the back plate of the capacitor is formed from a metal layer. A third and fourth dielectric layers surround the first two-layer conductive structure. A second two-layer equal potential conductive structure surrounds the third and fourth dielectric layers. In one embodiment, the second two-layer equal potential conductive structure comprise an interconnect between a metal layer and the substrate.

Abstract: Circuits, methods, and systems are disclosed in which a current is provided to compensate for spurious current while receiving signals through a line. For example, the spurious current can be sensed and the compensating current can be approximately equal to the sensed spurious current. The spurious current could include photocurrent from a bright light, and the compensating current can prevent bright light effects.

Abstract: Capacitance on a readout line is varied while receiving a signal, from a light sensing pixel or other sensing element through the line. Capacitance can be varied in accordance with a readout characteristic of the pixel, such as color sensed, conversion efficiency, or readout signal range. For example, a CMOS color image sensing array with pixels in an RGB Bayer pattern can include, for each column, a variable capacitance component with parallel switchable capacitors for signal sampling and readout sampling. The capacitors can all have equal values, or can be scaled in a binary format. The variable capacitance component can also include a constant capacitor. A controller can switch the capacitors to obtain capacitances that provide color equalization, and can use light level as well as pixel color for fine tuned color equalization. Sampled values from the capacitances can be provided in sequence to a readout amplifier at the beginning of a readout path to maintain signal-to-noise ratio.

Abstract: A reference voltage generator for use in an image sensor provides a reference voltage to an S/H block during a pixel read-out operation and another reference voltage to an analog-to-digital converter (ADC) during a digitization operation. The reference voltage generator includes a variable voltage generator, a sample-and-hold circuit to sample a reference voltage prior to the pixel read-out operation or the digitization operation, and a buffer amplifier to drive the appropriate reference voltage to the relatively high impedance load presented by the S/H block and the variable impedance load provided by the ADC.

Abstract: A reference voltage generator for use in an image sensor provides a reference voltage to an S/H block during a pixel read-out operation and another reference voltage to an analog-to-digital converter (ADC) during a digitization operation. The reference voltage generator includes a variable voltage generator, a sample-and-hold circuit to sample a reference voltage prior to the pixel read-out operation or the digitization operation, and a buffer amplifier to drive the appropriate reference voltage to the relatively high impedance load presented by the S/H block and the variable impedance load provided by the ADC.

Abstract: A reference voltage generator for use in an image sensor provides a reference voltage to an S/H block during a pixel read-out operation and another reference voltage to an analog-to-digital converter (ADC) during a digitization operation. The reference voltage generator includes a variable voltage generator, a sample-and-hold circuit to sample a reference voltage prior to the pixel read-out operation or the digitization operation, and a buffer amplifier to drive the appropriate reference voltage to the relatively high impedance load presented by the S/H block and the variable impedance load provided by the ADC.

Abstract: A voltage amplifier is provided. The voltage amplifier includes an amplifier stage to amplify an input signal. A bias current generator supplies a bias current to the amplifier stage. The bias current generator is controllable in response to a frame rate signal that is representative of a video frame rate. A compensation network stabilizes a loop response of the voltage amplifier. The compensation network is controllable in response to the frame rate signal.

Abstract: An apparatus such as an imager includes groups of sensors each of which includes subgroups of sensors. Subgroup select circuits are coupled to outputs from respective subgroups of sensors, and group select circuits are coupled to outputs from subgroup select circuits associated with respective ones of the groups. A bus is coupled to receive outputs from the group select circuits. A controller can provide control signals to the subgroup select circuits and the group select circuits to selectively enable the respective subgroup select circuits and group select circuits to pass signals from the sensors to the bus one sensor at a time.