Abstract: A variable resistance memory sense amplifier has a built-in offset to assist in switching the sense amplifier when a resistive memory cell is in a low resistance state. The built-in offset can be achieved by varying size, threshold voltage, associated capacity or associated resistance of the transistors within the sense amplifier.

Abstract: The present invention provides an improved write circuit and method for writing a programmable conductor random access memory (PCRAM) cell. The method comprises precharging a bit line to a first voltage and applying a second voltage to a first terminal of a chalcogenide memory element. A second terminal of the chalcogenide memory element is selectively coupled to the bit line to produce a voltage across the memory element sufficient to write a predetermined resistance state into the element. The first voltage may take on two different values to program two different resistance states into the memory element.

Abstract: A method and apparatus are provided for controlling refresh operations of a dynamic memory device. The temperature of the dynamic memory device is detected. The detected temperature is then used to adjust a refresh rate of the dynamic memory device to compensate for increased leakage at higher temperatures and more closely tailor the timing of the refresh operations to the conditions of the dynamic memory device.

Abstract: A temperature sensor is comprised of a device adapted to provide a first signal having a parameter responsive to temperature. A generator provides a reference signal having a parameter that is substantially consistent over a preselected temperature range. A comparator is electrically coupled to the device and the generator and is adapted to provide a second signal in response to the parameter of the first signal differing from the parameter of the reference signal. A digital filter is coupled to the comparator and is adapted to provide a third signal in response to receiving the second signal for a preselected duration of time.

Abstract: A sense circuit for reading a resistance level of a programmable conductor random access memory (PCRAM) cell is provided. A voltage potential difference is introduced across a PCRAM cell by activating an access transistor from a raised rowline voltage. Both a digit line and a digit complement reference line are precharged to a first predetermined voltage. The cell being sensed has the precharged voltage discharged through the resistance of the programmable conductor memory element of the PCRAM cell. A comparison is made of the voltage read at the digit line and at the reference conductor. If the voltage at the digit line is greater than the reference voltage, the cell is read as a high resistance value (e.g., logic HIGH); however, if the voltage measured at the digit line is lower than that of the reference voltage, the cell is read as a low resistance value (e.g., logic LOW).

Abstract: A method and apparatus are disclosed for sensing the resistance state of resistance-based memory element using complementary resistance-based elements, one holding the resistance state being sensed and the other holding a complementary resistance state. A sense amplifier detects voltages discharging through the high and low resistance elements to determine the resistance state of an element being read.

Abstract: A variable resistance memory sense amplifier has a built-in offset to assist in switching the sense amplifier when a resistive memory cell is in a low resistance state. The built-in offset can be achieved by varying size, threshold voltage, associated capacity or associated resistance of the transistors within the sense amplifier.

Abstract: This invention relates to MRAM technology and new variations on MRAM array architecture to incorporate certain advantages from both cross-point and 1T-1MTJ architectures. The fast read-time and higher signal-to-noise ratio of the 1T-1MTJ architecture and the higher packing density of the cross-point architecture are both exploited by combining certain characteristics of these layouts. A single access transistor 16 is used to read the multiple MRAM cells in a segment of a column, which can be stacked vertically above one another in a plurality of MRAM array layers arranged in a “Z” axis direction.

Abstract: A method and apparatus is disclosed for sensing the resistance state of a Programmable Conductor Random Access Memory (PCRAM) element using complementary PCRAM elements, one holding the resistance state being sensed and the other holding a complementary resistance state. A sense amplifier detects voltages discharging through the high and low resistance elements to determine the resistance state of an element being read.

Abstract: A sense circuit for reading a resistance level of a programmable conductor random access memory (PCRAM) cell is provided. A voltage potential difference is introduced across a PCRAM cell by activating an access transistor from a raised rowline voltage. Both a digit line and a digit complement reference line are precharged to a first predetermined voltage. The cell being sensed has the precharged voltage discharged through the resistance of the programmable conductor memory element of the PCRAM cell. A comparison is made of the voltage read at the digit line and at the reference conductor. If the voltage at the digit line is greater than the reference voltage, the cell is read as a high resistance value (e.g., logic HIGH); however, if the voltage measured at the digit line is lower than that of the reference voltage, the cell is read as a low resistance value (e.g., logic LOW).

Abstract: A circuit and method for producing a walking one pattern in a shift register. The circuit comprises a shift register and a NOR gate. The NOR gate output is connected to the data input of the shift register, and the data output of each of said register stages is connected to a respective one of the NOR gate inputs.

Abstract: This invention relates to MRAM technology and new variations on MRAM array architecture to incorporate certain advantages from both cross-point and 1T-1MTJ architectures. The fast read-time and higher signal-to-noise ratio of the 1T-1MTJ architecture and the higher packing density of the cross-point architecture are both exploited by combining certain characteristics of these layouts. A single access transistor 16 is used to read the multiple MRAM cells in a segment of a column, which can be stacked vertically above one another in a plurality of MRAM array layers arranged in a “Z” axis direction.

Abstract: The present invention provides a method and apparatus for writing a programmable conductor random access memory (PCRAM) element. After a read operation of the memory element a complement logical state from that read is written back to the memory element. In one embodiment the memory element is then again written back to its original state. In another embodiment logic circuitry keeps track of whether the original logic state or its complement are stored in the memory element so that during the next read the stored logic will be correctly read.

Abstract: A delay device is added to the addressing and refreshing circuitry of a DRAM array comprised of DRAM devices less volatile than conventional DRAM devices and, thus, need not be refreshed as often. The delay device is connected to intercept refresh signals generated by a conventional DRAM refresh controller and initiates a refresh cycle after disregarding a predetermined number of refresh signals generated by the refresh controller whose total duration equals the interval by which the less volatile DRAM devices must be refreshed. The delay device also is adapted to power off circuitry needed to address the DRAM devices when the DRAM devices are not being refreshed or otherwise accessed. Additional circuitry is added to selectively power on only specific addressing devices actually needed to address those certain portions of the array being refreshed at that time.

Abstract: This invention relates to MRAM technology and new variations on MRAM array architecture to incorporate certain advantages from both cross-point and 1T-1MTJ architectures. The fast read-time and higher signal-to-noise ratio of the 1T-1MTJ architecture and the higher packing density of the cross-point architecture are both exploited by combining certain characteristics of these layouts. A single access transistor 16 is used to read the multiple MRAM cells in a segment of a column, which can be stacked vertically above one another in a plurality of MRAM array layers arranged in a “Z” axis direction.

Abstract: The present invention provides a method and apparatus for writing a programmable conductor random access memory (PCRAM) element. After a read operation of the memory element a complement logical state from that read is written back to the memory element. In one embodiment the memory element is then again written back to its original state. In another embodiment logic circuitry keeps track of whether the original logic state or its complement are stored in the memory element so that during the next read the stored logic will be correctly read.

Abstract: A sense circuit and method for reading a resistance level of a programmable conductor memory element are provided. All rows and columns in a given memory array are initially held to the same potential. A desired row line is enabled by bringing it to approximately ground. The difference in voltage potential across a diode circuit of a selected cell activates the diodes and initiates current flow through the desired memory element of the desired cell. A column line associated with the cell is discharged from a precharge value through the diode circuit and memory element. The discharging voltage at the column line is compared with a reference voltage. If the voltage at the column line is greater than the reference voltage, then a high resistance level is detected, and, if the column line voltage is less than the reference voltage, a low resistance level is detected.

Abstract: A sense circuit for reading a resistance level of a programmable conductor random access memory (PCRAM) cell is provided. A voltage potential difference is introduced across a PCRAM cell by activating an access transistor from a raised rowline voltage. Both a digit line and a digit complement reference line are precharged to a first predetermined voltage. The cell being sensed has the precharged voltage discharged through the resistance of the programmable conductor memory element of the PCRAM cell. A comparison is made of the voltage read at the digit line and at the reference conductor. If the voltage at the digit line is greater than the reference voltage, the cell is read as a high resistance value (e.g., logic HIGH); however, if the voltage measured at the digit line is lower than that of the reference voltage, the cell is read as a low resistance value (e.g., logic LOW).

Abstract: The present invention provides an improved write circuit and method for writing a programmable conductor random access memory (PCRAM) cell. The method comprises precharging a bit line to a first voltage and applying a second voltage to a first terminal of a chalcogenide memory element. A second terminal of the chalcogenide memory element is selectively coupled to the bit line to produce a voltage across the memory element sufficient to write a predetermined resistance state into the element. The first voltage may take on two different values to program two different resistance states into the memory element.

Abstract: A method and apparatus is disclosed for sensing the resistance state of a Programmable Conductor Random Access Memory (PCRAM) element using complementary PCRAM elements, one holding the resistance state being sensed and the other holding a complementary resistance state. A sense amplifier detects voltages discharging through the high and low resistance elements to determine the resistance state of an element being read.