Abstract: A piezoelectronic transistor device includes a first piezoelectric (PE) layer, a second PE layer, and a piezoresistive (PR) layer arranged in a stacked configuration, wherein an electrical resistance of the PR layer is dependent upon an applied voltage across the first and second PE layers by an applied pressure to the PR layer by the first and second PE layers. A piezoelectronic logic device includes a first and second piezoelectric transistor (PET), wherein the first and second PE layers of the first PET have a smaller cross sectional area than those of the second PET, such that a voltage drop across the PE layers of the first PET creates a first pressure in the PR layer of the first PET that is smaller than a second pressure in the PR layer of the second PET created by the same voltage drop across the PE layers of the second PET.

Abstract: A piezoelectronic switch device for radio frequency (RF) applications includes a piezoelectric (PE) material layer and a piezoresistive (PR) material layer separated from one another by at least one electrode, wherein an electrical resistance of the PR material layer is dependent upon an applied voltage across the PE material layer by way of an applied pressure to the PR material layer by the PE material layer; and a conductive, high yield material (C-HYM) comprising a housing that surrounds the PE material layer, the PR material layer and the at least one electrode, the C-HYM configured to mechanically transmit a displacement of the PE material layer to the PR material layer such that applied voltage across the PE material layer causes an expansion thereof and an increase the applied pressure to the PR material layer, thereby causing a decrease in the electrical resistance of the PR material layer.

Abstract: A piezoelectronic transistor device includes a first piezoelectric (PE) layer, a second PE layer, and a piezoresistive (PR) layer arranged in a stacked configuration, wherein an electrical resistance of the PR layer is dependent upon an applied voltage across the first and second PE layers by an applied pressure to the PR layer by the first and second PE layers. A piezoelectronic logic device includes a first and second piezoelectric transistor (PET), wherein the first and second PE layers of the first PET have a smaller cross sectional area than those of the second PET, such that a voltage drop across the PE layers of the first PET creates a first pressure in the PR layer of the first PET that is smaller than a second pressure in the PR layer of the second PET created by the same voltage drop across the PE layers of the second PET.

Abstract: A piezoelectronic switch device for radio frequency (RF) applications includes a piezoelectric (PE) material layer and a piezoresistive (PR) material layer separated from one another by at least one electrode, wherein an electrical resistance of the PR material layer is dependent upon an applied voltage across the PE material layer by way of an applied pressure to the PR material layer by the PE material layer; and a conductive, high yield material (C-HYM) comprising a housing that surrounds the PE material layer, the PR material layer and the at least one electrode, the C-HYM configured to mechanically transmit a displacement of the PE material layer to the PR material layer such that applied voltage across the PE material layer causes an expansion thereof and an increase the applied pressure to the PR material layer, thereby causing a decrease in the electrical resistance of the PR material layer.

Abstract: A piezoelectronic transistor device includes a first piezoelectric (PE) layer, a second PE layer, and a piezoresistive (PR) layer arranged in a stacked configuration, wherein an electrical resistance of the PR layer is dependent upon an applied voltage across the first and second PE layers by an applied pressure to the PR layer by the first and second PE layers. A piezoelectronic logic device includes a first and second piezoelectric transistor (PET), wherein the first and second PE layers of the first PET have a smaller cross sectional area than those of the second PET, such that a voltage drop across the PE layers of the first PET creates a first pressure in the PR layer of the first PET that is smaller than a second pressure in the PR layer of the second PET created by the same voltage drop across the PE layers of the second PET.

Abstract: A piezoelectronic transistor device includes a first piezoelectric (PE) layer, a second PE layer, and a piezoresistive (PR) layer arranged in a stacked configuration, wherein an electrical resistance of the PR layer is dependent upon an applied voltage across the first and second PE layers by an applied pressure to the PR layer by the first and second PE layers. A piezoelectronic logic device includes a first and second piezoelectric transistor (PET), wherein the first and second PE layers of the first PET have a smaller cross sectional area than those of the second PET, such that a voltage drop across the PE layers of the first PET creates a first pressure in the PR layer of the first PET that is smaller than a second pressure in the PR layer of the second PET created by the same voltage drop across the PE layers of the second PET.

Abstract: A piezoelectronic switch device for radio frequency (RF) applications includes a piezoelectric (PE) material layer and a piezoresistive (PR) material layer separated from one another by at least one electrode, wherein an electrical resistance of the PR material layer is dependent upon an applied voltage across the PE material layer by way of an applied pressure to the PR material layer by the PE material layer; and a conductive, high yield material (C-HYM) comprising a housing that surrounds the PE material layer, the PR material layer and the at least one electrode, the C-HYM configured to mechanically transmit a displacement of the PE material layer to the PR material layer such that applied voltage across the PE material layer causes an expansion thereof and an increase the applied pressure to the PR material layer, thereby causing a decrease in the electrical resistance of the PR material layer.

Abstract: A nonvolatile memory storage device includes a ferroelectric (FE) material coupled with a piezoresistive (PR) material through an inherent piezoelectric response of the FE material, wherein an electrical resistance of the PR material is dependent on a compressive stress applied thereto, the compressive stress caused by a remanent strain of the FE material resulting from a polarization of the FE material, such that a polarized state of the FE material results in a first resistance value of the PR material, and a depolarized state of the FE material results in a second resistance value of the PR material.

Abstract: A piezoelectronic transistor device includes a first piezoelectric (PE) layer, a second PE layer, and a piezoresistive (PR) layer arranged in a stacked configuration, wherein an electrical resistance of the PR layer is dependent upon an applied voltage across the first and second PE layers by an applied pressure to the PR layer by the first and second PE layers. A piezoelectronic logic device includes a first and second piezoelectric transistor (PET), wherein the first and second PE layers of the first PET have a smaller cross sectional area than those of the second PET, such that a voltage drop across the PE layers of the first PET creates a first pressure in the PR layer of the first PET that is smaller than a second pressure in the PR layer of the second PET created by the same voltage drop across the PE layers of the second PET.

Abstract: A nonvolatile memory storage device includes a ferroelectric (FE) material coupled with a piezoresistive (PR) material through an inherent piezoelectric response of the FE material, wherein an electrical resistance of the PR material is dependent on a compressive stress applied thereto, the compressive stress caused by a remanent strain of the FE material resulting from a polarization of the FE material, such that a polarized state of the FE material results in a first resistance value of the PR material, and a depolarized state of the FE material results in a second resistance value of the PR material.

Abstract: A nanotube-graphene hybrid film and method for forming a cleaned nanotube-graphene hybrid film. The nanotube-graphene hybrid film includes a substrate; nanotube film deposited over the substrate to produce a layer of nanotube film; and graphene deposited over the layer of nanotube film to produce a nanotube-graphene hybrid film.

Abstract: A nanotube-graphene hybrid film and method for forming a cleaned nanotube-graphene hybrid film. A method includes depositing nanotube film over a metal foil to produce a layer of nanotube film, placing the metal foil with as-deposited nanotube film in a chemical vapor deposition furnace to grow graphene on the nanotube film to form a nanotube-graphene hybrid film, and transferring the nanotube-graphene hybrid film over a substrate.

Abstract: A nanotube-graphene hybrid nano-component and method for forming a cleaned nanotube-graphene hybrid nano-component. The nanotube-graphene hybrid nano-component includes a gate; a gate dielectric formed on the gate; a channel comprising a carbon nanotube-graphene hybrid nano-component formed on the gate dielectric; a source formed over a first region of the carbon nanotube-graphene hybrid nano-component; and a drain formed over a second region of the carbon nanotube-graphene hybrid nano-component to form a field effect transistor.

Abstract: A nanotube-graphene hybrid film and method for forming a cleaned nanotube-graphene hybrid film. The method includes depositing nanotube film over a substrate to produce a layer of nanotube film, removing impurities from a surface of the layer of nanotube film not contacting the substrate to produce a cleaned layer of nanotube film, depositing a layer of graphene over the cleaned layer of nanotube film to produce a nanotube-graphene hybrid film, and removing impurities from a surface of the nanotube-graphene hybrid film to produce a cleaned nanotube-graphene hybrid film, wherein the hybrid film has improved electrical performance. Another method includes depositing nanotube film over a metal foil to produce a layer of nanotube film, placing the metal foil with as-deposited nanotube film in a chemical vapor deposition furnace to grow graphene on the nanotube film to form a nanotube-graphene hybrid film, and transferring the nanotube-graphene hybrid film over a substrate.

Abstract: A graphene nanomesh based charge sensor and method for producing a graphene nanomesh based charge sensor. A graphene nanomesh based charge sensor includes a graphene nanomesh with a patterned array of multiple holes created by generating multiple holes in graphene in a periodic way, wherein: an edge of each of the multiple holes of the graphene nanomesh is passivated; and the passivated edge of each of the multiple holes of the graphene nanomesh is functionalized with a chemical compound that facilitates chemical binding of a receptor of a target molecule to the edge of one or more of the multiple holes, allowing the target molecule to bind to the receptor, causing a charge to be transferred to the graphene nanomesh to produce a graphene nanomesh based charge sensor for the target molecule.

Abstract: An apparatus and method for forming a patterned graphene layer on a substrate. One such method includes forming at least one patterned structure on a substrate; applying a layer of graphene on top of the at least one patterned structure on the substrate; heating the layer of graphene on top of the at least one patterned structure to remove one or more graphene regions proximate to the at least one patterned structure; and removing the at least one patterned structure to produce a patterned graphene layer on the substrate, wherein the patterned graphene layer on the substrate provides carrier mobility for electronic devices.

Abstract: A nonvolatile memory storage device includes a ferroelectric (FE) material coupled with a piezoresistive (PR) material through an inherent piezoelectric response of the FE material, wherein an electrical resistance of the PR material is dependent on a compressive stress applied thereto, the compressive stress caused by a remanent strain of the FE material resulting from a polarization of the FE material, such that a polarized state of the FE material results in a first resistance value of the PR material, and a depolarized state of the FE material results in a second resistance value of the PR material.

Abstract: A piezoelectronic device with novel force amplification includes a first electrode; a piezoelectric layer disposed on the first electrode; a second electrode disposed on the piezoelectric layer; an insulator disposed on the second electrode; a piezoresistive layer disposed on the insulator; a third electrode disposed on the insulator; a fourth electrode disposed on the insulator; a semi-rigid housing surrounding the layers and the electrodes; wherein the semi-rigid housing is in contact with the first, third, and fourth electrodes and the piezoresistive layer; wherein the semi-rigid housing includes a void. The third and fourth electrodes are on the same plane and separated from each other in the transverse direction by a distance.

Abstract: A graphene nanomesh based charge sensor and method for producing a graphene nanomesh based charge sensor. The method includes generating multiple holes in graphene to create a graphene nanomesh with a patterned array of multiple holes; passivating an edge of each of the multiple holes of the graphene nanomesh to allow for functionalization of the graphene nanomesh; and functionalizing the passivated edge of each of the multiple holes of the graphene nanomesh with a chemical compound that facilitates chemical binding of a receptor of a target molecule to the edge of one or more of the multiple holes, wherein the receptor is a molecule that chemically binds to the target molecule, irrespective of the size of the target molecule.

Abstract: Structures and methods for forming a patterned graphene layer on a substrate. One such method includes forming at least one patterned structure of a carbide-forming metal or metal-containing alloy on a substrate, applying a layer of graphene on top of the at least one patterned structure of a carbide-forming metal or metal-containing alloy on the substrate, heating the layer of graphene on top of the at least one patterned structure of a carbide-forming metal or metal-containing alloy in an environment to remove graphene regions proximate to the at least one patterned structure of a carbide-forming metal or metal-containing alloy, and removing the at least one patterned structure of a carbide-forming metal or metal-containing alloy to produce a patterned graphene layer on the substrate, wherein the patterned graphene layer on the substrate provides carrier mobility for electronic devices.