Patents by Inventor Greg A. Blodgett
Greg A. Blodgett has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20130272075Abstract: A memory chip design methodology is disclosed wherein fuse banks on the memory chip may be implemented without enable fuses. A fuse bank may be enabled by using one or more least significant bits (LSBs) in the memory address stored in the fuse bank, thereby avoiding the need for a separate enable fuse. A reduction in the number of fuses results in space savings on the memory chip real estate and also savings in power consumption because of fewer fuses to be blown and read. With reduced fuse count, the yield of the memory chip's die may also be improved because of less number of defective fuses or failed fuse blows. The use of effective default state inversion for address fuses may further reduce the average number of fuses that need to be blown to repair a given non-redundant memory address. Because of the rules governing abstracts, this abstract should not be used to construe the claims.Type: ApplicationFiled: June 6, 2013Publication date: October 17, 2013Inventor: Greg Blodgett
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Patent number: 8497699Abstract: Techniques for controlling a driver to reduce data dependent noise, such as simultaneous switching effects and cross-talk effects. A plurality of drivers may each receive a data segment to transmit and a plurality of data segments that other drivers will transmit. A driver controller may adjust the time at which the data segment is transmitted in response to the plurality of data segments that the other drivers will transmit. The adjustment may compensate for simultaneous switching noise and cross-talk by, for example, delaying the transmission of a data segment or changing the slew rate of the signal carrying the data segment.Type: GrantFiled: June 6, 2011Date of Patent: July 30, 2013Assignee: Micron Technology, Inc.Inventors: Chang Ki Kwon, Greg A. Blodgett
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Patent number: 8462570Abstract: A memory chip design methodology is disclosed wherein fuse banks on the memory chip may be implemented without enable fuses. A fuse bank may be enabled by using one or more least significant bits (LSBs) in the memory address stored in the fuse bank, thereby avoiding the need for a separate enable fuse. A reduction in the number of fuses results in space savings on the memory chip real estate and also savings in power consumption because of fewer fuses to be blown and read. With reduced fuse count, the yield of the memory chip's die may also be improved because of less number of defective fuses or failed fuse blows. The use of effective default state inversion for address fuses may further reduce the average number of fuses that need to be blown to repair a given non-redundant memory address. Because of the rules governing abstracts, this abstract should not be used to construe the claims.Type: GrantFiled: September 11, 2009Date of Patent: June 11, 2013Assignee: Micron Technology, Inc.Inventor: Greg Blodgett
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Publication number: 20130055046Abstract: Apparatuses and memory refresh methods are disclosed, such as those involving checking a portion of a memory device for errors in response to the memory device being powered on, and reprogramming corrected data to the memory device if errors are found in checking the portion of the nonvolatile memory for errors. Other apparatuses and memory refresh methods are disclosed.Type: ApplicationFiled: August 31, 2011Publication date: February 28, 2013Inventor: Greg A. Blodgett
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Publication number: 20130010538Abstract: A block repair device is used in a Dynamic Random Access Memory (DRAM) having a primary array with a defective cell and a redundant array with a redundant row. The block repair device stores a block repair configuration that determines the dimensions (e.g., the number of rows and columns spanned) of a repair block. Routing circuitry is configured by the stored block repair configuration to output some row and column address bits from received row and column addresses in a selected ratio. Comparison circuitry compares the row and column address bits output by the routing circuitry with the address of the defective cell that defines the repair block. When a match occurs, the comparison circuitry implements a block repair by activating the redundant row and by causing data to be written to or read from the activated redundant row instead of the primary array.Type: ApplicationFiled: September 13, 2012Publication date: January 10, 2013Applicant: MOSAID Technologies IncorporatedInventor: Greg A. Blodgett
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Patent number: 8296606Abstract: A block repair device is used in a Dynamic Random Access Memory (DRAM) having a primary array with a defective cell and a redundant array with a redundant row. The block repair device stores a block repair configuration that determines the dimensions (e.g., the number of rows and columns spanned) of a repair block. Routing circuitry is configured by the stored block repair configuration to output some row and column address bits from received row and column addresses in a selected ratio. Comparison circuitry compares the row and column address bits output by the routing circuitry with the address of the defective cell that defines the repair block. When a match occurs, the comparison circuitry implements a block repair by activating the redundant row and by causing data to be written to or read from the activated redundant row instead of the primary array.Type: GrantFiled: December 30, 2010Date of Patent: October 23, 2012Assignee: Mosaid Technologies IncorporatedInventor: Greg A. Blodgett
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Publication number: 20120201090Abstract: A system and method are disclosed to accomplish power savings in an electronic device, such as a memory chip, by performing selective frequency locking and subsequent instantaneous frequency switching in the DLL (delay locked loop) used for clock synchronization in the electronic device. By locking the DLL at a slow clock frequency, the operational frequency may be substantially instantaneously switched to an integer-multiplied frequency of the initial locking frequency without losing the DLL lock point. This DLL locking methodology allows for faster frequency changes from higher (during normal operation) to lower (during a power saving mode) clock frequencies without resorting to gradual frequency slewing to conserve power and maintain DLL locking. Hence, a large power reduction may be accomplished substantially instantaneously without adding complexity to the system clock generator. Because of the rules governing abstracts, this abstract should not be used in construing the claims.Type: ApplicationFiled: April 18, 2012Publication date: August 9, 2012Applicant: Micron Technology, Inc.Inventors: Greg A. Blodgett, Tyler Gomm
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Patent number: 8164368Abstract: A system and method are disclosed to accomplish power savings in an electronic device, such as a memory chip, by performing selective frequency locking and subsequent instantaneous frequency switching in the DLL (delay locked loop) used for clock synchronization in the electronic device. By locking the DLL at a slow clock frequency, the operational frequency may be substantially instantaneously switched to an integer-multiplied frequency of the initial locking frequency without losing the DLL lock point. This DLL locking methodology allows for faster frequency changes from higher (during normal operation) to lower (during a power saving mode) clock frequencies without resorting to gradual frequency slewing to conserve power and maintain DLL locking. Hence, a large power reduction may be accomplished substantially instantaneously without adding complexity to the system clock generator. Because of the rules governing abstracts, this abstract should not be used in construing the claims.Type: GrantFiled: April 19, 2005Date of Patent: April 24, 2012Assignee: Micron Technology, Inc.Inventors: Greg A. Blodgett, Tyler Gomm
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Publication number: 20110234257Abstract: Techniques for controlling a driver to reduce data dependent noise, such as simultaneous switching effects and cross-talk effects. A plurality of drivers may each receive a data segment to transmit and a plurality of data segments that other drivers will transmit. A driver controller may adjust the time at which the data segment is transmitted in response to the plurality of data segments that the other drivers will transmit. The adjustment may compensate for simultaneous switching noise and cross-talk by, for example, delaying the transmission of a data segment or changing the slew rate of the signal carrying the data segment.Type: ApplicationFiled: June 6, 2011Publication date: September 29, 2011Applicant: Micron Technology, Inc.Inventors: Chang Ki Kwon, Greg A. Blodgett
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Patent number: 7982494Abstract: Embodiments of the present invention include systems for calibrating an output circuit. A comparator is coupled to a calibration terminal and configured to determine whether the calibration terminal is in a first state coupled to a calibration resistor or in a second state. A calibration circuit is coupled to the calibration terminal and configured to generate a calibration value based in part on the presence or absence of the calibration resistor. An impedance selector is coupled to the calibration circuit, the comparator, and a default calibration value. The impedance selector is configured to select the default calibration value when the comparator indicates the calibration terminal is in the second state and to select the calibration value coupled from the calibration circuit when the comparator indicates the calibration terminal is in the first state.Type: GrantFiled: March 3, 2010Date of Patent: July 19, 2011Assignee: Micron Technology, Inc.Inventors: Raghu Sreeramaneni, Vijay Vankayala, Greg Blodgett
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Patent number: 7956648Abstract: Techniques for controlling a driver to reduce data dependent noise, such as simultaneous switching effects and cross-talk effects. A plurality of drivers may each receive a data segment to transmit and a plurality of data segments that other drivers will transmit. A driver controller may adjust the time at which the data segment is transmitted in response to the plurality of data segments that the other drivers will transmit. The adjustment may compensate for simultaneous switching noise and cross-talk by, for example, delaying the transmission of a data segment or changing the slew rate of the signal carrying the data segment.Type: GrantFiled: March 25, 2009Date of Patent: June 7, 2011Assignee: Micron Technology, Inc.Inventors: Chang Ki Kwon, Greg A. Blodgett
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Patent number: 7936181Abstract: An off chip driver impedance adjustment circuit includes a storage circuit adapted to receive and store a drive strength adjustment word. A counter circuit is coupled to the storage circuit to receive the drive strength adjustment word and develops a drive strength count responsive to the drive strength adjustment word. A programmable fuse code to preset the counter. An output driver circuit is coupled to the counter circuit to receive the drive strength count and is adapted to receive a data signal. The output driver circuit develops an output signal on an output responsive to the data signal and adjusts a drive strength as a function of the drive strength count.Type: GrantFiled: December 5, 2008Date of Patent: May 3, 2011Assignee: Round Rock Research, LLCInventors: Greg A. Blodgett, Christopher K. Morzano
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Publication number: 20110099417Abstract: A block repair device is used in a Dynamic Random Access Memory (DRAM) having a primary array with a defective cell and a redundant array with a redundant row. The block repair device stores a block repair configuration that determines the dimensions (e.g., the number of rows and columns spanned) of a repair block. Routing circuitry is configured by the stored block repair configuration to output some row and column address bits from received row and column addresses in a selected ratio. Comparison circuitry compares the row and column address bits output by the routing circuitry with the address of the defective cell that defines the repair block. When a match occurs, the comparison circuitry implements a block repair by activating the redundant row and by causing data to be written to or read from the activated redundant row instead of the primary array.Type: ApplicationFiled: December 30, 2010Publication date: April 28, 2011Inventor: Greg A. Blodgett
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Patent number: 7872926Abstract: An input buffer having a comparator that receives an input signal, a reference signal and a positive feedback. The comparator compares the input signal relative to the reference signal and generates an output signal transitioning between a first logic state and a second logic state responsive to the magnitude of the input signal transitioning through the magnitude of the reference signal. The comparator intensifies the output signal in response to the positive feedback from the output of the comparator while the output signal transitions from the first logic state to the second logic state.Type: GrantFiled: June 26, 2009Date of Patent: January 18, 2011Assignee: Micron Technology, Inc.Inventor: Greg Blodgett
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Patent number: 7870435Abstract: A block repair device is used in a Dynamic Random Access Memory (DRAM) having a primary array with a defective cell and a redundant array with a redundant row. The block repair device stores a block repair configuration that determines the dimensions (e.g., the number of rows and columns spanned) of a repair block. Routing circuitry is configured by the stored block repair configuration to output some row and column address bits from received row and column addresses in a selected ratio. Comparison circuitry compares the row and column address bits output by the routing circuitry with the address of the defective cell that defines the repair block. When a match occurs, the comparison circuitry implements a block repair by activating the redundant row and by causing data to be written to or read from the activated redundant row instead of the primary array.Type: GrantFiled: December 16, 2008Date of Patent: January 11, 2011Assignee: Mosaid Technologies IncorporatedInventor: Greg A. Blodgett
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Publication number: 20100182014Abstract: Embodiments of the present invention include systems for calibrating an output circuit. A comparator is coupled to a calibration terminal and configured to determine whether the calibration terminal is in a first state coupled to a calibration resistor or in a second state. A calibration circuit is coupled to the calibration terminal and configured to generate a calibration value based in part on the presence or absence of the calibration resistor. An impedance selector is coupled to the calibration circuit, the comparator, and a default calibration value. The impedance selector is configured to select the default calibration value when the comparator indicates the calibration terminal is in the second state and to select the calibration value coupled from the calibration circuit when the comparator indicates the calibration terminal is in the first state.Type: ApplicationFiled: March 3, 2010Publication date: July 22, 2010Applicant: Micron Technology, Inc.Inventors: Raghu Sreeramaneni, Vijay Vankayala, Greg Blodgett
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Patent number: 7696778Abstract: Embodiments of the present invention include systems for calibrating an output circuit. A comparator is coupled to a calibration terminal and configured to determine whether the calibration terminal is in a first state coupled to a calibration resistor or in a second state. A calibration circuit is coupled to the calibration terminal and configured to generate a calibration value based in part on the presence or absence of the calibration resistor. An impedance selector is coupled to the calibration circuit, the comparator, and a default calibration value. The impedance selector is configured to select the default calibration value when the comparator indicates the calibration terminal is in the second state and to select the calibration value coupled from the calibration circuit when the comparator indicates the calibration terminal is in the first state.Type: GrantFiled: January 16, 2009Date of Patent: April 13, 2010Assignee: Micron Technology, Inc.Inventors: Raghu Sreeramaneni, Vijay Vankayala, Greg Blodgett
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Publication number: 20100002530Abstract: A memory chip design methodology is disclosed wherein fuse banks on the memory chip may be implemented without enable fuses. A fuse bank may be enabled by using one or more least significant bits (LSBs) in the memory address stored in the fuse bank, thereby avoiding the need for a separate enable fuse. A reduction in the number of fuses results in space savings on the memory chip real estate and also savings in power consumption because of fewer fuses to be blown and read. With reduced fuse count, the yield of the memory chip's die may also be improved because of less number of defective fuses or failed fuse blows. The use of effective default state inversion for address fuses may further reduce the average number of fuses that need to be blown to repair a given non-redundant memory address. Because of the rules governing abstracts, this abstract should not be used to construe the claims.Type: ApplicationFiled: September 11, 2009Publication date: January 7, 2010Inventor: Greg Blodgett
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Publication number: 20090262585Abstract: An input buffer having a comparator that receives an input signal, a reference signal and a positive feedback. The comparator compares the input signal relative to the reference signal and generates an output signal transitioning between a first logic state and a second logic state responsive to the magnitude of the input signal transitioning through the magnitude of the reference signal. The comparator intensifies the output signal in response to the positive feedback from the output of the comparator while the output signal transitions from the first logic state to the second logic state.Type: ApplicationFiled: June 26, 2009Publication date: October 22, 2009Applicant: Micron Technology, Inc.Inventor: Greg Blodgett
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Patent number: 7606102Abstract: A memory chip design methodology is disclosed wherein fuse banks on the memory chip may be implemented without enable fuses. A fuse bank may be enabled by using one or more least significant bits (LSBs) in the memory address stored in the fuse bank, thereby avoiding the need for a separate enable fuse. A reduction in the number of fuses results in space savings on the memory chip real estate and also savings in power consumption because of fewer fuses to be blown and read. With reduced fuse count, the yield of the memory chip's die may also be improved because of less number of defective fuses or failed fuse blows. The use of effective default state inversion for address fuses may further reduce the average number of fuses that need to be blown to repair a given non-redundant memory address. Because of the rules governing abstracts, this abstract should not be used to construe the claims.Type: GrantFiled: August 24, 2006Date of Patent: October 20, 2009Assignee: Micron Technology, Inc.Inventor: Greg Blodgett