Abstract: A system is described which uses a burst access memory and a memory controller to anticipate the memory address to be used in future data read operations as requested by a microprocessor. Either the memory controller or the memory device initiates a burst read operation starting at a memory address generated thereby. The microprocessor can, therefore, wait to initiate a data read without suffering a time delay.

Abstract: A negative word line driver employs devices to maintain the potential difference between the active word line signal and the inactive word line signal while reducing the need for a significant negative voltage supply. One form of the negative word line driver employs an isolation element to couple the word line to ground when the inputs to the word line driver indicate the word line should not be active, while the word line is also coupled to the negative voltage supply. Another form of the form of the negative word line driver receives as inputs the voltages to be driven on the word line and can be implemented with fewer transistors but still allows the word line to be driven at a negative voltage with a reduced negative voltage supply.

Abstract: A memory chip design methodology is disclosed wherein fuse banks on the memory chip may be implemented without enable fuses. A fuse bank may be enabled by using one or more least significant bits (LSBs) in the memory address stored in the fuse bank, thereby avoiding the need for a separate enable fuse. A reduction in the number of fuses results in space savings on the memory chip real estate and also savings in power consumption because of fewer fuses to be blown and read. With reduced fuse count, the yield of the memory chip's die may also be improved because of less number of defective fuses or failed fuse blows. The use of effective default state inversion for address fuses may further reduce the average number of fuses that need to be blown to repair a given non-redundant memory address. Because of the rules governing abstracts, this abstract should not be used to construe the claims.

Abstract: Techniques for controlling a driver to reduce data dependent noise, such as simultaneous switching effects and cross-talk effects. A plurality of drivers may each receive a data segment to transmit and a plurality of data segments that other drivers will transmit. A driver controller may adjust the time at which the data segment is transmitted in response to the plurality of data segments that the other drivers will transmit. The adjustment may compensate for simultaneous switching noise and cross-talk by, for example, delaying the transmission of a data segment or changing the slew rate of the signal carrying the data segment.

Abstract: A memory device, delay lock loop circuit (DLL) and DLL reset circuitry are described. The DLL includes a shift register and a measured delay for pre-loading the shift register. The reset circuitry selectively filters a clock signal propagation through the measured delay during a reset operation.

Abstract: An antifuse latch device and method for performing a redundancy pretest without the use of additional test circuitry is disclosed. Conventional antifuse latch devices are designed such that a redundancy pretest cannot be performed on the antifuse latch device once the antifuses are programmed but rather requires additional circuitry to map the appropriate address bits to test the redundant row or column. The present invention adds a level translating inverter to a conventional antifuse latch device, thus allowing the antifuse latch device to simulate an unblown antifuse by isolating the antifuse from the latch.

Abstract: A clock synchronization circuit receives an input clock signal along with current and future data signals. The clock synchronization circuit generates a phase shifted clock signal in response to the input clock signal, with the phase shifted clock signal having a phase shift relative to the input clock signal that is a function of the current and future data signals. The clock synchronization circuit may also generate a plurality of phase shifted clock signals, with each phase shifted clock signal having a respective phase shift that is a function of the current and future logic states of groups of the other data signals.

Abstract: A method of operating a delay locked loop is comprised of producing a first output signal in response to a first lock point. A new lock point is measured, or otherwise determined, while continuing to produce the first output signal. Thereafter, a second output signal is produced in response to the new lock point. The new lock point data may be loaded into the delay locked loop while the delay locked loop continues to produce the first output signal. The delay locked loop switches from producing the first output signal, responsive to a first lock point, to producing the second output signal, responsive to the new lock point, in response to various conditions such as control signals, e.g. an auto refresh command, a precharge all command, a mode register load command, a power down entry, a power down exit (among others), in response to a timer, e.g., an internal timer (among others), or in response to environmental condition signals, e.g., a temperature sensor output signal (among others).

Abstract: A system and method are disclosed to accomplish power savings in an electronic device, such as a memory chip, by performing selective frequency locking and subsequent instantaneous frequency switching in the DLL (delay locked loop) used for clock synchronization in the electronic device. By locking the DLL at a slow clock frequency, the operational frequency may be substantially instantaneously switched to an integer-multiplied frequency of the initial locking frequency without losing the DLL lock point. This DLL locking methodology allows for faster frequency changes from higher (during normal operation) to lower (during a power saving mode) clock frequencies without resorting to gradual frequency slewing to conserve power and maintain DLL locking. Hence, a large power reduction may be accomplished substantially instantaneously without adding complexity to the system clock generator. Because of the rules governing abstracts, this abstract should not be used in construing the claims.

Abstract: The present invention allows for the reduction in power consumption of memory devices. A memory device in one embodiment prohibits address signal propagation on internal address buses based upon a function being performed by the memory. As such, some, all or none of the externally provided address signals are allowed to transition past address buffer circuitry.

Abstract: A memory chip design methodology is disclosed wherein fuse banks on the memory chip may be implemented without enable fuses. A fuse bank may be enabled by using one or more least significant bits (LSBs) in the memory address stored in the fuse bank, thereby avoiding the need for a separate enable fuse. A reduction in the number of fuses results in space savings on the memory chip real estate and also savings in power consumption because of fewer fuses to be blown and read. With reduced fuse count, the yield of the memory chip's die may also be improved because of less number of defective fuses or failed fuse blows. The use of effective default state inversion for address fuses may further reduce the average number of fuses that need to be blown to repair a given non-redundant memory address. Because of the rules governing abstracts, this abstract should not be used to construe the claims.

Abstract: An antifuse latch device and method for performing a redundancy pretest without the use of additional test circuitry is disclosed. Conventional antifuse latch devices are designed such that a redundancy pretest cannot be performed on the antifuse latch device once the antifuses are programmed but rather requires additional circuitry to map the appropriate address bits to test the redundant row or column. The present invention adds a level translating inverter to a conventional antifuse latch device, thus allowing the antifuse latch device to simulate an unblown antifuse by isolating the antifuse from the latch.

Abstract: A clock synchronization circuit receives an input clock signal along with current and future data signals. The clock synchronization circuit generates a phase shifted clock signal in response to the input clock signal, with the phase shifted clock signal having a phase shift relative to the input clock signal that is a function of the current and future data signals. The clock synchronization circuit may also generate a plurality of phase shifted clock signals, with each phase shifted clock signal having a respective phase shift that is a function of the current and future logic states of groups of the other data signals.

Abstract: A method and system for operating a DRAM device in either a high power, full density mode or a low power, half density mode. In the full density mode, each data bit is stored in a single memory cell, and, in the half density mode, each data bit is stored in two memory cells that are refreshed at the same time to permit a relatively slow refresh rate. When transitioning from the full density mode to the half density mode, data are copied from each row of memory cells storing data to an adjacent row of memory cells. The adjacent row of memory cells are made free to store data from an adjacent row by remapping the most significant bit of the row address to the least significant bit of the row address, and then remapping all of the remaining bits of the row address to the next highest order bit.

Abstract: A power saving circuit disables input buffers for command and address signals during an auto-refresh of a DRAM. The input buffers are re-enabled at the end of the auto-refresh in a manner that does not cause spurious commands to be generated. The power saving circuit prevents spurious commands by biasing internal command signals to a “no operation” command whenever the input buffers for the command signals are disabled. The DRAM may also be placed in a mode in which it automatically transitions to a low power precharge mode at the end of the auto-refresh to further reduce power consumed by the DRAM.

Abstract: A method and system for operating a DRAM device in either a high power, full density mode or a low power, half density mode. In the full density mode, each data bit is stored in a single memory cell, and, in the half density mode, each data bit is stored in two memory cells that are refreshed at the same time to permit a relatively slow refresh rate. When transitioning from the full density mode to the half density mode, data are copied from each row of memory cells storing data to an adjacent row of memory cells. The adjacent row of memory cells are made free to store data from an adjacent row by remapping the most significant bit of the row address to the least significant bit of the row address, and then remapping all of the remaining bits of the row address to the next highest order bit.

Abstract: An off chip driver impedance adjustment circuit includes a storage circuit adapted to receive and store a drive strength adjustment word. A counter circuit is coupled to the storage circuit to receive the drive strength adjustment word and develops a drive strength count responsive to the drive strength adjustment word. A programmable fuse code to preset the counter. An output driver circuit is coupled to the counter circuit to receive the drive strength count and is adapted to receive a data signal. The output driver circuit develops an output signal on an output responsive to the data signal and adjusts a drive strength as a function of the drive strength count.

Abstract: An off chip driver impedance adjustment circuit includes a storage circuit adapted to receive and store a drive strength adjustment word. A counter circuit is coupled to the storage circuit to receive the drive strength adjustment word and develops a drive strength count responsive to the drive strength adjustment word. A programmable fuse code to preset the counter. An output driver circuit is coupled to the counter circuit to receive the drive strength count and is adapted to receive a data signal. The output driver circuit develops an output signal on an output responsive to the data signal and adjusts a drive strength as a function of the drive strength count.

Abstract: A system is described which uses a burst access memory and a memory controller to anticipate the memory address to be used in future data read operations as requested by a microprocessor. Either the memory controller or the memory device initiates a burst read operation starting at a memory address generated thereby. The microprocessor can, therefore, wait to initiate a data read without suffering a time delay.

Abstract: A memory chip design methodology is disclosed wherein fuse banks on the memory chip may be implemented without enable fuses. A fuse bank may be enabled by using one or more least significant bits (LSBs) in the memory address stored in the fuse bank, thereby avoiding the need for a separate enable fuse. A reduction in the number of fuses results in space savings on the memory chip real estate and also savings in power consumption because of fewer fuses to be blown and read. With reduced fuse count, the yield of the memory chip's die may also be improved because of less number of defective fuses or failed fuse blows. The use of effective default state inversion for address fuses may further reduce the average number of fuses that need to be blown to repair a given non-redundant memory address. Because of the rules governing abstracts, this abstract should not be used to construe the claims.