Abstract: A negative word line driver employs devices to maintain the potential difference between the active word line signal and the inactive word line signal while reducing the need for a significant negative voltage supply. One form of the negative word line driver employs an isolation element to couple the word line to ground when the inputs to the word line driver indicate the word line should not be active, while the word line is also coupled to the negative voltage supply. Another form of the form of the negative word line driver receives as inputs the voltages to be driven on the word line and can be implemented with fewer transistors but still allows the word line to be driven at a negative voltage with a reduced negative voltage supply.

Abstract: The present invention allows for the reduction in power consumption of memory devices. A memory device in one embodiment prohibits address signal propagation on internal address buses based upon a function being performed by the memory. As such, some, all or none of the externally provided address signals are allowed to transition past address buffer circuitry.

Abstract: A programmable circuit and its method of operation are disclosed in which a transistor is used as a programmable element. The transistor may be programmed to one of two different gate threshold voltage values for operation. During reading of the transistor, a gate threshold voltage between the two values is applied and the status of the transistor as on or off is determined to determine the program state of the transistor. The program state of the transistor can be determined by a simple latch circuit.

Abstract: A fuse read sequence for a memory device obtains enhanced energy efficiency by selectively reading or strobing antifuse or fuse circuit banks of the memory device in response to operational commands of the memory device. More particularly, the column antifuse circuit banks of an SDRAM are read in response to a load mode register command and the row and option antifuse circuit banks are read in response to auto refresh commands. Furthermore, only half of the row/option antifuse circuit banks are read on each auto refresh command.

Abstract: A multiphase charge pump including first and second phase charge pump circuits. Each of the first and second phase charge pump circuits includes a bootstrap capacitor. The bootstrap capacitors are switchingly connected by an equalization circuit that periodically transfers charge from a discharging capacitor to a charging capacitor, thereby reducing the charge that must be externally supplied to charge the charging capacitor.

Abstract: A power saving circuit disables input buffers for command and address signals during an auto-refresh of a DRAM. The input buffers are re-enabled at the end of the auto-refresh in a manner that does not cause spurious commands to be generated. The power saving circuit prevents spurious commands by biasing internal command signals to a “no operation” command whenever the input buffers for the command signals are disabled. The DRAM may also be placed in a mode in which it automatically transitions to a low power precharge mode at the end of the auto-refresh to further reduce power consumed by the DRAM.

Abstract: A method and system for operating a DRAM device in either a high power, full density mode or a low power, half density mode. In the full density mode, each data bit is stored in a single memory cell, and, in the half density mode, each data bit is stored in two memory cells that are refreshed at the same time to permit a relatively slow refresh rate. When transitioning from the full density mode to the half density mode, data are copied from each row of memory cells storing data to an adjacent row of memory cells. The adjacent row of memory cells are made free to store data from an adjacent row by remapping the most significant bit of the row address to the least significant bit of the row address, and then remapping all of the remaining bits of the row address to the next highest order bit.

Abstract: A method and system for operating a DRAM device in either a high power, full density mode or a low power, half density mode. In the full density mode, each data bit is stored in a single memory cell, and, in the half density mode, each data bit is stored in two memory cells that are refreshed at the same time to permit a relatively slow refresh rate. When transitioning from the full density mode to the half density mode, data are copied from each row of memory cells storing data to an adjacent row of memory cells. The adjacent row of memory cells are made free to store data from an adjacent row by remapping the most significant bit of the row address to the least significant bit of the row address, and then remapping all of the remaining bits of the row address to the next highest order bit.

Abstract: A voltage pump and method of driving a node to an increased potential. A periodic input signal is fed into a precharged small capacitor to create a level shifted periodic intermediate potential at an intermediate node. The intermediate node is a supply node to a level translator circuit. The output of the level translator circuit controls the actuation of a pass transistor. When actuated the pass transistor drives a boosted potential to an output node of the voltage pump circuit. In one embodiment the level translator circuit has a delay element which maintains the deactivation of a pull down portion of the level translator circuit until a pull up portion of the level translator circuit is deactivated. A first diode clamp is used to limit the output of the level translator circuit and the boosted potential to within 1 threshold voltage (of the diode clamp) of each other.

Abstract: A multiphase charge pump including first and second phase charge pump circuits. Each of the first and second phase charge pump circuits includes a bootstrap capacitor. The bootstrap capacitors are switchingly connected by an equalization circuit that periodically transfers charge from a discharging capacitor to a charging capacitor, thereby reducing the charge that must be externally supplied to charge the charging capacitor.

Abstract: A programmable circuit and its method of operation are disclosed in which a transistor is used as a programmable element. The transistor may be programmed to one of two different gate threshold voltage values for operation. During reading of the transistor, a gate threshold voltage between the two values is applied and the status of the transistor as on or off is determined to determine the program state of the transistor. The program state of the transistor can be determined by a simple latch circuit.

Abstract: A negative word line driver employs devices to maintain the potential difference between the active word line signal and the inactive word line signal while reducing the need for a significant negative voltage supply. One form of the negative word line driver employs an isolation element to couple the word line to ground when the inputs to the word line driver indicate the word line should not be active, while the word line is also coupled to the negative voltage supply. Another form of the form of the negative word line driver receives as inputs the voltages to be driven on the word line and can be implemented with fewer transistors but still allows the word line to be driven at a negative voltage with a reduced negative voltage supply.

Abstract: A lower current input buffer is used for waking up a plurality of higher-current buffers. The lower current buffer monitors a wake-up signal and, when present, enables the higher current buffers. A higher current buffer is used to detect the sleep mode and disable the higher current buffers. A delay circuit may be used to balance the propagation delay through the circuit.

Abstract: The present invention comprises memory devices, including multiple bit per cell memory cells and methods for operating same. The multiple bit per cell memory cells of the present invention have higher memory densities than conventional single bit per cell memory cells. Additionally, spare states in multiple bit per cell memory devices that remain unmapped to binary data bits may be advantageously used.

Abstract: A memory device with a segmented column architecture that allows for single bank repair across any two row blocks is disclosed. Multiple redundant columns are provided that have offset segment boundaries, i.e., a first redundant column is divided into four segments consisting of row block <0,1>, row block <2,3>, row block <4,5> and row block <6,7>, and a second redundant column is divided into four segments consisting of row block <1,2>, row block <3,4>, row block <5,6> and row block <0,7>. By offsetting the segment boundaries, the repair of the memory device can be optimized by repairing any two adjacent row blocks with only one column segment by selecting the appropriate redundant column segment.

Abstract: The present invention comprises a memory array including multiple bit per cell memory cells and methods for operating same. The multiple bit per cell memory cells of the present invention have higher memory densities than conventional single bit per cell memory cells. Additionally, spare states in multiple bit per cell memory devices that remain unmapped to binary data bits may be advantageously used.

Abstract: A fuse read sequence for a memory device is disclosed. The fuse read sequence obtains enhanced energy efficiency by selectively reading or strobing antifuse or fuse circuit banks of the memory device in response to operational commands of the memory device. More particularly, the column antifuse circuit banks of a SDRAM are read in response to a load mode register command and the row and option antifuse circuit banks are read in response to auto refresh commands. Furthermore, only half of the row/option antifuse circuit banks are read on each auto refresh command.

Abstract: A method and system for operating a DRAM device in either a high power, full density mode or a low power, half density mode. In the full density mode, each data bit is stored in a single memory cell, and, in the half density mode, each data bit is stored in two memory cells that are refreshed at the same time to permit a relatively slow refresh rate. When transitioning from the full density mode to the half density mode, data are copied from each row of memory cells storing data to an adjacent row of memory cells. The adjacent row of memory cells are made free to store data from an adjacent row by remapping the most significant bit of the row address to the least significant bit of the row address, and then remapping all of the remaining bits of the row address to the next highest order bit.

Abstract: The present invention allows for the reduction in power consumption of memory devices. A memory device in one embodiment prohibits address signal propagation on internal address buses based upon a function being performed by the memory. As such, some, all or none of the externally provided address signals are allowed to transition past address buffer circuitry.

Abstract: The present invention comprises memory devices, apparatuses and systems including multiple bit per cell memory cells and methods for operating same. The multiple bit per cell memory cells of the present invention have higher memory densities than conventional single bit per cell memory cells. Additionally, spare states in multiple bit per cell memory devices that remain unmapped to binary data bits may be advantageously used.