Abstract: A fuse read sequence for a memory device obtains enhanced energy efficiency by selectively reading or strobing antifuse or fuse circuit banks of the memory device in response to operational commands of the memory device. More particularly, the column antifuse circuit banks of an SDRAM are read in response to a load mode register command and the row and option antifuse circuit banks are read in response to auto refresh commands. Furthermore, only half of the row/option antifuse circuit banks are read on each auto refresh command.

Abstract: A DRAM sense amplifier that reduces the leakage current through the sense amplifier circuitry while the array is active, while controlling the body voltage of the sense amplifier transistors to improve performance of the sense amplifier circuitry is disclosed. The body nodes of the sense amplifier transistors are pre-charged to a voltage potential, such as for example Vcc/2. The body nodes are disconnected from the pre-charge voltage while the sense amplifier is enabled, i.e., during an access operation, but the threshold voltage Vt of the sense amplifier transistors will be lower during sensing due to the pre-charge level. As the body potential drops during sensing, the threshold voltage Vt will increase, thereby reducing the leakage current that flows through the sense amplifier while the digit lines are separated.

Abstract: A multiphase charge pump including first and second phase charge pump circuits. Each of the first and second phase charge pump circuits includes a bootstrap capacitor. The bootstrap capacitors are switchingly connected by an equalization circuit that periodically transfers charge from a discharging capacitor to a charging capacitor, thereby reducing the charge that must be externally supplied to charge the charging capacitor.

Abstract: A block repair device is used in a Dynamic Random Access Memory (DRAM) having a primary array with a defective cell and a redundant array with a redundant row. The block repair device stores a block repair configuration that determines the dimensions (e.g., the number of rows and columns spanned) of a repair block. Routing circuitry is configured by the stored block repair configuration to output some row and column address bits from received row and column addresses in a selected ratio. Comparison circuitry compares the row and column address bits output by the routing circuitry with the address of the defective cell that defines the repair block. When a match occurs, the comparison circuitry implements a block repair by activating the redundant row and by causing data to be written to or read from the activated redundant row instead of the primary array.

Abstract: A programmable circuit and its method of operation are disclosed in which a transistor is used as a programmable element. The transistor may be programmed to one of two different gate threshold voltage values for operation. During reading of the transistor, a gate threshold voltage between the two values is applied and the status of the transistor as on or off is determined to determine the program state of the transistor. The program state of the transistor can be determined by a simple latch circuit.

Abstract: The present invention comprises memory devices, including multiple bit per cell memory cells and methods for operating same. The multiple bit per cell memory cells of the present invention have higher memory densities than conventional single bit per cell memory cells. Additionally, spare states in multiple bit per cell memory devices that remain unmapped to binary data bits may be advantageously used.

Abstract: A system is described which uses a burst access memory and a memory controller to anticipate the memory address to be used in future data read operations as requested by a microprocessor. Either the memory controller or the memory device initiates a burst read operation starting at a memory address generated thereby. The microprocessor can, therefore, wait to initiate a data read without suffering a time delay.

Abstract: A clock synchronization circuit receives an input clock signal along with current and future data signals. The clock synchronization circuit generates a phase shifted clock signal in response to the input clock signal, with the phase shifted clock signal having a phase shift relative to the input clock signal that is a function of the current and future data signals. The clock synchronization circuit may also generate a plurality of phase shifted clock signals, with each phase shifted clock signal having a respective phase shift that is a function of the current and future logic states of groups of the other data signals.

Abstract: An antifuse latch device and method for performing a redundancy pretest without the use of additional test circuitry is disclosed. Conventional antifuse latch devices are designed such that a redundancy pretest cannot be performed on the antifuse latch device once the antifuses are programmed but rather requires additional circuitry to map the appropriate address bits to test the redundant row or column. The present invention adds a level translating inverter to a conventional antifuse latch device, thus allowing the antifuse latch device to simulate an unblown antifuse by isolating the antifuse from the latch.

Abstract: The present invention comprises memory devices, apparatuses and systems including multiple bit per cell memory cells and methods for operating same. The multiple bit per cell memory cells of the present invention have higher memory densities than conventional single bit per cell memory cells. Additionally, spare states in multiple bit per cell memory devices that remain unmapped to binary data bits may be advantageously used.

Abstract: A memory device with a segmented column architecture that allows for single bank repair across any two row blocks is disclosed. Multiple redundant columns are provided that have offset segment boundaries, i.e., a first redundant column is divided into four segments consisting of row block <0,1>, row block <2,3>, row block <4,5> and row block <6,7>, and a second redundant column is divided into four segments consisting of row block <1,2>, row block <3,4>, row block <5,6> and row block <0,7>. By offsetting the segment boundaries, the repair of the memory device can be optimized by repairing any two adjacent row blocks with only one column segment by selecting the appropriate redundant column segment.

Abstract: A fuse read sequence for a memory device obtains enhanced energy efficiency by selectively reading or strobing antifuse or fuse circuit banks of the memory device in response to operational commands of the memory device. More particularly, the column antifuse circuit banks of an SDRAM are read in response to a load mode register command and the row and option antifuse circuit banks are read in response to auto refresh commands. Furthermore, only half of the row/option antifuse circuit banks are read on each auto refresh command.

Abstract: A block repair device is used in a Dynamic Random Access Memory (DRAM) having a primary array with a defective cell and a redundant array with a redundant row. The block repair device includes a set of fuses, anti-fuses, or flash EEPROM cells that store a block repair configuration that determines the dimensions (e.g., the number of rows and columns spanned) of a repair block used to repair the defective cell. Routing circuitry, such as mux circuitry, in the block repair device is configured by the stored block repair configuration to output some row and column address bits from received row and column addresses in a selected ratio. Comparison circuitry in the block repair device then compares the row and column address bits output by the routing circuitry with a stored portion of the address of the defective cell that defines the repair block.

Abstract: A voltage pump and method of driving a node to an increased potential. A periodic input signal is fed into a precharged small capacitor to create a level shifted periodic intermediate potential at an intermediate node. The intermediate node is a supply node to a level translator circuit The output of the level translator circuit controls the actuation of a pass transistor. When actuated the pass transistor drives a boosted potential to an output node of the voltage pump circuit. In one embodiment the level translator circuit has a delay element which maintains the deactivation of a pull down portion of the level translator circuit until a pull up portion of the level translator circuit is deactivated. A first diode clamp is used to limit the output of the level translator circuit and the boosted potential to within 1 threshold voltage (of the diode clamp) of each other.

Abstract: A power saving circuit disables input buffers for command and address signals during an auto-refresh of a DRAM. The input buffers are re-enabled at the end of the auto-refresh in a manner that does not cause spurious commands to be generated. The power saving circuit prevents spurious commands by biasing internal command signals to a “no operation” command whenever the input buffers for the command signals are disabled. The DRAM may also be placed in a mode in which it automatically transitions to a low power precharge mode at the end of the auto-refresh to further reduce power consumed by the DRAM.

Abstract: An antifuse latch device and method for performing a redundancy pretest without the use of additional test circuitry is disclosed. Conventional antifuse latch devices are designed such that a redundancy pretest cannot be performed on the antifuse latch device once the antifuses are programmed but rather requires additional circuitry to map the appropriate address bits to test the redundant row or column. The present invention adds a level translating inverter to a conventional antifuse latch device, thus allowing the antifuse latch device to simulate an unblown antifuse by isolating the antifuse from the latch.

Abstract: A high speed data path includes a first plurality of inverters skewed toward one logic level alternating with a second plurality of inverters skewed toward a second logic level. As a result, the inverters in the first plurality accelerate one transition of a digital signal and the inverters in the second plurality accelerate the opposite transition of the digital signal. Prior to applying the digital signal to the inverters, the inverters are preset to a logic level from which they will transition in an accelerated manner. As a result, a transition of the digital signal is coupled through the inverters in an accelerated manner.

Abstract: A dynamic random access memory device uses a gray code counter to generate addresses in a self-refresh operating mode so that only one bit of a row address generated by the counter changes state from one refresh cycle to the next. The row addresses are applied to a row address pre-decoder that coupled pre-decoded row address signals to a memory array in the memory device. The row address pre-decoder is operable to continuously couple at least some of the pre-decoded row address signals to the array from one refresh cycle to the next. As a result, only one a plurality of signal lines coupling the pre-decoded row address signals to the array must change state from one refresh cycle to the next, thereby minimizing the power consumed during the self-refresh mode.

Abstract: A dynamic random access memory device uses a gray code counter to generate addresses in a self-refresh operating mode so that only one bit of a row address generated by the counter changes state from one refresh cycle to the next. The row addresses are applied to a row address pre-decoder that coupled pre-decoded row address signals to a memory array in the memory device. The row address pre-decoder is operable to continuously couple at least some of the pre-decoded row address signals to the array from one refresh cycle to the next. As a result, only one a plurality of signal lines coupling the pre-decoded row address signals to the array must change state from one refresh cycle to the next, thereby minimizing the power consumed during the self-refresh mode.

Abstract: A DRAM sense amplifier that reduces the leakage current through the sense amplifier circuitry while the array is active, while controlling the body voltage of the sense amplifier transistors to improve performance of the sense amplifier circuitry is disclosed. The body nodes of the sense amplifier transistors are pre-charged to a voltage potential, such as for example Vcc/2. The body nodes are disconnected from the pre-charge voltage while the sense amplifier is enabled, i.e., during an access operation, but the threshold voltage Vt of the sense amplifier transistors will be lower during sensing due to the pre-charge level. As the body potential drops during sensing, the threshold voltage Vt will increase, thereby reducing the leakage current that flows through the sense amplifier while the digit lines are separated.