Abstract: Example implementations relate to a memory controller. For example, an apparatus includes a data storage device and a memory controller coupled to the data storage device. The memory controller is to perform, during a memory scrubbing operation, a corrective action to correct an error associated with a data block stored in the data storage device. The memory control is to determine, during the memory scrubbing operation, whether the corrective action is successful. In response to a determination that the corrective action is a failed corrective action, the memory controller is to fix a hardware failure of the data storage device based on a type of the hardware failure.

Abstract: According to an example, hierarchal stripe locks may be obtained for a source stripe and a destination stripe. In response to receiving data for the source stripe, the data is written from the source stripe to the destination stripe, and the hierarchal stripe locks are released for the source stripe and the destination stripe. In response to receiving the data-migrated token, the hierarchal stripe locks are released for the source stripe and the destination stripe.

Abstract: According to an example, a lock may be requested by a first redundancy controller from a parity media controller to perform a first sequence that accesses multiple memory modules in a stripe. The lock may be acquired for the stripe so that the first sequence may be performed on the stripe. The lock may then be released from the stripe.

Abstract: Techniques for updating data in a reflective memory region of a first memory device are described herein. In one example, a method for updating data in a reflective memory region of a first memory device includes receiving an indication that data is to be flushed from a cache device to the first memory device. The method also includes detecting a memory address corresponding to the data is within the reflective memory region of the first memory device and sending data from the cache device to the first memory device with a flush operation. Additionally, the method includes determining that the data received by the first memory device is modified data. Furthermore, the method includes sending the modified data to a second memory device in a second computing system.

Abstract: A memristor memory is disclosed. In an example, the memristor memory comprises a memristor component having a plurality of memristor cells. Each memristor cell is configured to change state based on application of an electric potential. The memristor memory also comprises a controller to read the state of the plurality of memristor cells and identify a subset of the plurality of memristor cells to rewrite. The controller writes the subset of the plurality of memristor cells, and the controller reads an updated state of the plurality of memristor cells to validate the subset was written correctly.

Abstract: A system for re-initializing a memory array is described. The system includes a processor and a memory array communicatively coupled to the processor. The system also includes a memory manager. The memory manager includes an establish module to establish a reference state for the memory array. The reference state includes a number of target resistance values for the memory array. The memory manager includes a write module to write data to the memory array. The memory manager includes a re-initialize module to re-initialize the memory array to the established reference state.

Abstract: A method for managing data using a number of non-volatile memory arrays is described. The method includes writing data from a volatile memory region to a first non-volatile memory array. The method also includes writing a remaining portion of the data from the volatile memory region to a second non-volatile memory array in response to detecting that an event has occurred. The second non-volatile memory array has a lower write latency than the first non-volatile memory array.

Abstract: A device includes a cross-point array and an access circuit to access subsets of memory elements respectively corresponding to encoded blocks of data. For each of the subsets of memory elements, a row or a column of the cross-point array that includes a first memory element in the subset and a second memory element in the subset further includes a third memory element that is between the first and second memory elements along the row or column and is in one of the subsets corresponding to another of the encoded blocks.

Abstract: A method for encoding data in a memory array is described. The method includes receiving data to be stored in the memory array. The method also includes encoding the data, to generate a number of encoded data versions. The method also includes selecting, based on a number of optimization heuristics, which of a number of data versions to store in the memory array. The number of data versions include the number of encoded data versions and the data. The method also includes indicating, in metadata associated with the data, the selected data version. The method also includes writing the selected data version, the metadata, or combination thereof, to the memory array.

Abstract: A method for identifying memory regions that contain remapped memory locations is described. The method includes determining, from a number of tracking bits on a memory module controller, whether a memory region comprises a remapped memory location. The method further includes performing a remapped memory operation on the memory region based on the determination, wherein memory within a computing device is divided into a number of memory regions including the memory region.

Abstract: A method for remapping a memory location in a memory array is described. The method includes receiving, by a memory manager, an identification of a first memory location in a memory array that is to be remapped using a remapping procedure performed by a memory manager. The remapping procedure includes selecting a second memory location to store data intended for the first memory location. The procedure also includes writing, in the first memory location, a pointer to the second memory location.

Abstract: A non-volatile memory device with multiple latency tiers includes at least two crossbar memory arrays, each crossbar memory array comprising a number of memory cells, each memory cell connected to a word line and a bit line at a cross point. The crossbar memory arrays each have a different latency. The crossbar memory arrays are formed on a single die.

Abstract: A method for managing a multi-lane serial link is described. The method includes establishing a serial link between a number of integrated circuits across a first number of lanes. The first number of lanes are a subset of a number of available lanes on the serial link. The method also includes selecting to change a transmission state of a second number of lanes. The second number of lanes are a subset of the available lanes. The method also includes changing the transmission state of the second number of lanes while transmitting data on a number of remaining lanes. The method further includes synchronizing the first number of lanes and the second number of lanes.

Abstract: Example implementations relate to managing data on a memory module. Data may be transferred between a first NVM and a second NVM on a memory module. The second NVM may have a higher memory capacity and a longer access latency than the first NVM. A mapping between a first address and a second address may be stored in an NVM on the memory module. The first address may refer to a location at which data is stored in the first NVM. The second address may refer to a location, in the second NVM, from which the data was copied.

Abstract: Examples disclosed herein provide moving a block of data between a source address and a target address. The examples disclose initiating a data move engine to move the block of data from the source address to the target address. Additionally, the examples disclose moving the block of data from the source address to the target address in a manner which allows a processor to concurrently access the block of data during the move.

Abstract: Example embodiments relate to response control for memory modules that include or interface with non-compliant memory technologies. A memory module may include an interface to a memory bus that complies with a data transfer standard, wherein the memory bus communicates with a memory controller, and an interface to a non-compliant memory technology that does not comply with the data transfer standard. The memory module may include a command monitoring circuit to determine whether a command from the memory controller has been or will be completed by the non-compliant memory circuit within a defined amount of time within which a command should be completed according to the data transfer standard. The memory module may include an error causing circuit that signals to the memory controller or an operating system when the command has not or will not complete within the defined amount of time.

Abstract: A completion packet may be returned before a data packet is written to a memory, if a field of the data packet indicates the data packet was sent due to a cache capacity eviction. The completion packet is returned after the data packet is written to the memory, if the field indicates the data packet was sent due to a flush operation.

Abstract: First and second read requests are received. First data is fetched in response to the first read request. The fetched first data is then stored. The fetched first data corresponds to an address of the first read request. The fetched first data is returned in response to the second read request.

Abstract: A computing system can include a processor and a persistent main memory including a fault tolerance capability. The computing system can also include a memory controller to store data in the persistent main memory and create redundant data. The memory controller can also store the redundant data remotely with respect to the persistent main memory. The memory controller can further access the redundant data during failure of the persistent main memory.

Abstract: Example embodiments relate to write flow control for memory modules that include or interface with non-compliant memory technologies. A memory module may include an interface to a memory bus and a memory controller that comply with a data transfer standard. The memory module may include a write buffer to receive write commands from the interface to the memory bus. The write buffer may cause the write commands to be transmitted to the non-compliant memory technology using a communication protocol that does not comply with the data transfer standard. The memory module may include a flow control credit counter to monitor the capacity of the write buffer, and to provide a credit count to the memory controller that indicates the number of write commands that the write buffer can accept.