Abstract: A system and method for loopback self testing. A system includes a host device and an endpoint device. The host device transmits unencoded test symbols. The endpoint device loops back the unencoded test symbols to the host device. The host device drives at least some bits of each unencoded test symbol onto host device data signals and drives at least some bits of each unencoded test symbol onto host device control signals.

Abstract: Systems and methods are provided to manage access to computing resources. More specifically, certain embodiments are described in which a resource or resource consumer can engage access controls or request that access controls be engaged if the age of a request exceeds one or more thresholds. For example, a requester may, after the age of a request meets or exceeds a threshold, indicate to a destination that a control should be engaged.

Abstract: An upstream-communication end node of an apparatus in an example upon a receipt of an indication of threshold-partial fullness of transaction-storage space on a downstream-communication end node modifies transaction-selection for delivery to the downstream-communication end node to exclude one or more transactions originated on the upstream-communication end node.

Abstract: A method is disclosed for handling interruptions, such as asynchronous interrupts, of a process using a system resource. The method determines whether a process is currently using a system resource. If a resource is being used and the system receives an interruption, then the method logs the interruption and delays accepting the interruption until after the process currently using the resource is completed. The method may be implemented in a system that controls access of processes to resources using semaphores that lock the resources while in use. The method determines whether a resource is currently in use by detecting a load and clear operation, indicating that a semaphore has locked the resource. The method delays acceptance of the interruption until either a branch command is executed, a store command is executed, a specified number of instructions are retired, or a specified number of clock cycles pass.

Abstract: An embodiment of the invention provides a circuit and method for reducing power in multi-way set associative arrays. A control circuit detects when the next cache access will be taken from the same cache way that the previous cache access was taken from. If the next cache access is taken from the same cache way as the previous cache access, the control circuit signals all the cache ways, except the cache way that was previously accessed, to not access information from their arrays. The control circuit also signals the tag arrays to not access their information and disables power to all the compare circuits. In this manner, power may be reduced when sequentially accessing information from one cache way in a multi-way set associative array.

Abstract: Speculative pre-fetching and pre-flushing of additional cache lines minimize cache miss latency and coherency check latency of an out of order instruction execution processor. A pre-fetch/pre-flush slot (DPRESLOT) is provided in a memory queue (MQUEUE) of the out-of-order execution processor. The DPRESLOT monitors the transactions between a system interface, e.g., the system bus, and an address reorder buffer slot (ARBSLOT) and/or between the system interface and a cache coherency check slot (CCCSLOT). When a cache miss is detected, the DPRESLOT causes one or more cache lines in addition to the data line, which caused the current cache miss, to be pre-fetched from the memory hierarchy into the cache memory (DCACHE) in anticipation that the additional data would be required in the near future.

Abstract: A method for determining which way of an N-way set associative cache should be filled with replacement data upon generation of a cache miss when all of the ways contain valid data. A first choice for way selection and at least one additional choice for way selection are generated. If the status of the way corresponding to the first choice differs from a bias status, a way corresponding to one of the additional choices is designated as the way to be filled with replacement data. Otherwise, the way corresponding to the first choice is designated as the way to be filled with replacement data. Status information for a given way may include any data which is maintained on a cache line by cache line basis, but is preferably data which is maintained for purposes other than way selection. For example, status information might include indications as to whether a cache line is shared or private, clean or dirty.

Abstract: A method is disclosed for handling interruptions, such as asynchronous interrupts, of a process using a system resource. The method determines whether a process is currently using a system resource. If a resource is being used and the system receives an interruption, then the method logs the interruption and delays accepting the interruption until after the process currently using the resource is completed. The method may be implemented in a system that controls access of processes to resources using semaphores that lock the resources while in use. The method determines whether a resource is currently in use by detecting a load and clear operation, indicating that a semaphore has locked the resource. The method delays acceptance of the interruption until either a branch command is executed, a store command is executed, a specified number of instructions are retired, or a specified number of clock cycles pass.

Abstract: A method for determining which way of an N-way set associative cache should be filled with replacement data upon generation of a cache miss when all of the ways contain valid data. A first choice for way selection and at least one additional choice for way selection are generated. If the status of the way corresponding to the first choice differs from a bias status, a way corresponding to one of the additional choices is designated as the way to be filled with replacement data. Otherwise, the way corresponding to the first choice is designated as the way to be filled with replacement data. Status information for a given way may include any data which is maintained on a cache line by cache line basis, but is preferably data which is maintained for purposes other than way selection. For example, status information might include indications as to whether a cache line is shared or private, clean or dirty.

Abstract: Speculative pre-fetching and pre-flushing of additional cache lines minimize cache miss latency and coherency check latency of an out of order instruction execution processor. A pre-fetch/pre-flush slot (DPRESLOT) is provided in a memory queue (MQUEUE) of the out-of-order execution processor. The DPRESLOT monitors the transactions between a system interface, e.g., the system bus, and an address reorder buffer slot (ARBSLOT) and/or between the system interface and a cache coherency check slot (CCCSLOT). When a cache miss is detected, the DPRESLOT causes one or more cache lines in addition to the data line, which caused the current cache miss, to be pre-fetched from the memory hierarchy into the cache memory (DCACHE) in anticipation that the additional data would be required in the near future.

Abstract: A method for determining which way of an N-way set associative cache should be filled with replacement data upon generation of a cache miss when all of the ways contain valid data. A first choice for way selection and at least one additional choice for way selection are generated. If the status of the way corresponding to the first choice differs from a bias status, a way corresponding to one of the additional choices is designated as the way to be filled with replacement data. Otherwise, the way corresponding to the first choice is designated as the way to be filled with replacement data. Status information for a given way may include any data which is maintained on a cache line by cache line basis, but is preferably data which is maintained for purposes other than way selection. For example, status information might include indications as to whether a cache line is shared or private, clean or dirty.

Abstract: Circuitry for providing external access to signals that are internal to an integrated circuit chip package. A plurality of N:1 multiplexers are physically distributed throughout the integrated circuit die. Each of the multiplexers has its N inputs coupled to a nearby set of N nodes within the integrated circuit, and each of the multiplexers is coupled to a source of select information operable to select one node from the set of N nodes for external access. Each of the multiplexers has its output coupled to an externally-accessible chip pad. The integrated circuit is a microprocessor, and the source of select information may include a storage element. If so, additional circuitry is provided for writing data from a register of the microprocessor to the storage element using one or more microprocessor instructions. Each multiplexer may be coupled to a different source of select information, or all multiplexers may be coupled to the same select information.

Abstract: Method of processing information in a microprocessor. At a first time during the life cycle of an instruction, a first set of microprocessor self-monitoring information is generated. The first set of mnicroprocessor self-monitoring information is stored, information necessary to execute the instruction is stored, and the two are associated. At a second time during the life cycle of the instruction, a second set of microprocessor self-monitoring information may be generated. This is also stored and is associated with the information necessary to execute the instruction. If the instruction retires, the first and second information may be retrieved for use in microprocessor testing. The information may also be used as soon as it is generated, for example by communicating the information itself or indicators derived from it to a state machine configured to facilitate microprocessor testing.

Abstract: In one embodiment, the invention includes a method of tracking events in a microprocessor that can retire more than one instruction during a clock cycle. A set of match results is generated during each clock cycle, one match result for each retiring instruction. Each of the match results indicates whether the corresponding retiring instruction matched a criterion. Then, the total number of retiring instruction that matched the criterion is determined by adding the asserted match results to generate a sum. A counter is incremented by the sum. In another embodiment, the invention includes circuitry for implementing the just-described method. Match generator circuitry is provided for generating a set of match results during each clock cycle, one match result for each retiring instruction. The outputs of the match generator circuitry are supplied to adder circuitry.

Abstract: Circuitry for detecting signal patterns on a multi-bit bus. First comparison circuitry monitors a first portion of the bus comparing it with a first expected signal pattern, generating a first comparison output. Second comparison circuitry monitors a second portion of the bus comparing it with a second expected signal pattern, generating a second comparison output. Both comparison outputs are applied to an AND gate and a first OR gate. One data input of a multiplexer is coupled to the output of the first OR gate. Another data input is coupled to the output of the AND gate. Another data input is coupled to the first comparison output, and another data input is coupled to the second comparison output.One input of a second OR gate may be coupled to the multiplexer output, and another input coupled to a disable indicator, allowing the multiplexer output to be overridden.

Abstract: User-configurable diagnostic hardware contained on-chip with a microprocessor for the purpose of debugging and monitoring the performance of the microprocessor. Method for using the same. A programmable state machine is coupled to on-chip and off-chip input sources. The state machine may be programmed to look for signal patterns presented by the input sources, and to respond to the occurrence of a defined pattern (or sequence of defined patterns) by driving certain control information onto a state machine output bus. On-chip devices coupled to the output bus take user-definable actions as dictated by the bus. The input sources include user-configurable comparators located within the functional blocks of the microprocessor. The comparators are coupled to storage elements within the microprocessor, and are configured to monitor nodes to determine whether the state of the nodes matches the data contained in the storage elements.

Abstract: An operand dependency tracking system tracks move-to-space (MTSP) operand dependencies among instructions in a processor that executes instructions out of order. Instructions are forwarded from an instruction fetch mechanism to a reordering mechanism, where the instructions are permitted to execute out of order. After execution of an instruction by an execution unit, instructions are retired by a retire mechanism, which transforms the results of instruction execution to the architecture state. While instructions are executed in the reordering mechanism, the operand dependency tracking system detects an MTSP instruction and a load instruction. The MTSP instruction is destined to modify data in a space register that stores virtual address information. The load instruction is controlled to commence execution after the MTSP instruction commences execution. While executing the load instruction, the tracking system determines whether the load instruction is destined to use the data in the space register.

Abstract: A recovery method for each instruction in an instruction queue comprises steps of monitoring a launch bus to determine when an instruction has executed and comparing the tag number of the launched instruction with the tag numbers of the instructions upon which the instruction in the queue depends. After all dependencies for the instruction in the queue have cleared, a flag is set to indicate that the instruction is ready to launch. Even though all dependencies have cleared and the flag is set, the instruction in the queue still monitors the tag bus to check whether an instruction upon which it depends ever reexecutes. In the case that the instruction does reexecute, the instruction in the queue once again sets its flag to indicate that it is ready to launch, whereby the instruction in the queue will also reexecute.

Abstract: A method and apparatus is disclosed for reading data from and writing data to remote registers that are dispersed throughout an integrated circuit chip. Regardless of the size or number of remote registers involved, the operation is accomplished using only two interconnect lines, plus a clock. Each remote register is associated with a unique address. During a write operation, a microprocessor loads the write data into a staging register, loads the destination address into a header generation register along with a read/write control bit, and loads a count value into a clock. Thereafter, the apparatus of the invention proceeds automatically, as the clock counts down, to shift the data onto a serial data line following a header. Each of the remote registers in the system are arranged serially, and each monitors the header information, comparing the address contained in the header with its own address.