Abstract: Analog memory-based activation function for an artificial neural network can be provided. An apparatus can include at least two non-volatile memory devices connected in parallel such that the current can flow through one of the two non-volatile memory devices depending on the voltage level driving the current. To control which branch an input current flows through, each of the two non-volatile memory devices can be connected to a circuit element that can function as a switch, for example, a diode such as a semiconductor diode, a transistor, or another circuit element. Such apparatus can implement an analog memory-based activation function, for example, for an analog memory-based artificial neural network.

Abstract: The exemplary embodiments disclose an apparatus, a system and method, and a computer program product for removing dental plaque. The exemplary embodiments may include emitting light, detecting reflections of the light, analyzing the reflected light, and determining an amount or location of dental plaque based on the reflected light.

Abstract: A semiconductor device includes a ferroelectric random-access memory (FeRAM) cell. The FeRAM includes a ferroelectric dielectric that is annealed to attain its ferroelectric phase by an induced current flow and heating process. The current flow may be induced though a temporary wire that causes heating of the FeRAM cell. The resulting heating or anneal of the ferroelectric dielectric may crystalize the ferroelectric dielectric to embody or result in having ferroelectric properties. The induced current flow and heating process is substantially local to the FeRAM cell, and to ferroelectric dielectric therein, as opposed to a global heating or annealing process in which the entire semiconductor device, or a relatively larger region of semiconductor device, is heated to the requisite annealing temperature of ferroelectric dielectric.

Abstract: A semiconductor device includes a plurality of seed structures disposed in a dielectric layer. The plurality of seed structures are spaced apart from each other. Respective ones of the plurality of seed structures have a tapered shape with a decreasing width from an upper surface of the dielectric layer, and include semiconductor crystalline material.

Abstract: A computer program product for training a machine learning model. A processor executes program instructions stored on a computer readable media to perform a forward pass read by applying a bias input voltage to a gate of a first resistive processing unit (RPU) configured for infrequent writes and storing a first conductance value representing a synaptic weight value to read from the first RPU a product of the bias input voltage and the first conductance value. The processor performs a backward pass to compute a loss value for the forward pass read and to compute a gradient value to minimize the loss value. The processor applies a coercive input voltage to a gate of a second RPU configured differently for frequent writes to write to the second RPU a second conductance value related to the gradient value and representing a gradient accumulation value.

Abstract: Techniques for imparting tensile stress in NFET devices are provided. In one aspect, an exemplary FET device includes: a channel layer disposed on a substrate, where the channel layer has both horizontal and vertical portions, and where the vertical portions of the channel layer connect adjacent ones of the horizontal portions; a gate surrounding the channel layer (i.e., in a gate-all-around configuration); and source/drain regions on opposite ends of the channel layer. Portions of the gate can be present between the horizontal portions of the channel layer. A method of fabricating the present FET devices is also provided.

Abstract: Aspects of the invention include a semiconductor structure including a ferroelectric field effect transistor (FeFET) and a ferroelectric capacitor (FeCAP) on a substrate. The FeFET including a first channel portion of the substrate, an oxide interfacial layer on the first channel portion of the substrate, a crystalline ferroelectric dielectric on the oxide interfacial layer; and an upper electrode on the crystalline ferroelectric dielectric. The FeCAP including a second channel portion of the substrate, the crystalline ferroelectric dielectric on and in contact with the second channel portion of the substrate, a lower electrode on the crystalline ferroelectric dielectric wherein the lower electrode comprises a scavenging material and an upper electrode on the lower electrode. The FeCAP and FeFET can be part of a cross-bar array in which the FeCAP functions as a gradient accumulation device and the FeFET functions as a weight storage device.

Abstract: A solid-state switch structure including a first solid-state material having a programable electrical resistance comprising a high electrical resistance obtained following a first type programming pulse and a low electrical resistance obtained following a second type programming pulse, a second solid-state material having a programable electrical resistance comprising a high electrical resistance obtained following said second type programming pulse and a low electrical resistance obtained following said first type programming pulse, a first contact made to a first end of said first solid-state material, a second contact made to a first end of said second solid-state material, a third contact made to a second end of said first solid-state material and to a second end of said second solid-state material.

Abstract: A vertical ferroelectric field effect transistor includes a source, a drain, and a channel in a channel opening vertically connecting the source and the drain. On either side of the channel are an alternating stack of a plurality of insulator layers and a plurality of metal electrodes. A cover insulator is over the alternating stack while the source is over and in contact with a top surface of the cover insulator. A ferroelectric layer is between and in contact with each of the plurality of metal electrodes and a portion of the channel sidewalls.

Abstract: A cross-point array includes an array of Resistive Processing Unit (RPU) devices having rows and columns interconnected at cross-points, wherein the RPU devices receive a finite duration input voltage on the rows and output a current on the columns. An input-signal matched filter is coupled to each of the columns to reduce noise in the current in accordance with the finite duration input voltage.

Abstract: An interconnect structure including conducting layers of topological semi-metals and/or topological insulators. To increase charge carrier density in the conducting layers, a charge carrier doping layer present on at least one surface of the one or more conductive layers of topological semi-metals. The charge carrying doping layers have a charge carrier density greater than the topological semi-metals and/or topological insulators of the one or more conductive layers.

Abstract: A device structure for a phase-change memory device is disclosed. The device structure includes a top electrode, a phase-change material that is recessed between two layers of resistive liner material, and a conductive material. The conductive material contacts the sidewall of the top electrode, the sidewall of the phase-change material, and a portion of a top surface and a bottom surface of each of the two layers of the resistive liner material. The device structure includes a heater contacting a bottom electrode and the bottom layer of the resistive liner material. The heater is in a first bilayer dielectric. A second bilayer dielectric is under the top electrode.

Abstract: A non-volatile memory apparatus includes a first hydrogen reservoir, which is electrically conductive; a charge of hydrogen, which is captured in the first hydrogen reservoir; a dielectric layer that has a first side that is adjacent to the first hydrogen reservoir and a second side that is opposite from the first hydrogen reservoir; a second hydrogen reservoir that is adjacent to the second side of the dielectric layer, is electrically conductive, and has a side that is opposite from the dielectric layer; and a piezoelectric layer that is adjacent to the side of the second hydrogen reservoir and that has a side that is opposite from the second hydrogen reservoir.

Abstract: An electronic device includes a first electrode, a second electrode, and a memory component configured to store a resistive state. The memory component includes a layered region arranged in direct contact with the first electrode and a bulk region arranged in direct contact with the second electrode. The layered region includes a plurality of first layers made of a first material and a plurality of second layers made of a second material alternatingly arranged with one another. The first material is a phase-change material and the second material is a non-phase-change material. The bulk region is a continuous mass made of a third material that is different than the first material and the second material, and the bulk region is in direct contact with at least two of the first layers and at least one of the second layers of the layered region.

Abstract: A phase-change memory device is disclosed. The phase-change memory device includes a heater electrode having an uppermost surface. The phase-change memory device further includes a phase-change layer having a lowermost surface in direct contact with the uppermost surface of the heater electrode at a first location. The phase-change memory device further includes an outer electrode contact arm in direct contact with the phase-change layer at a second location that is spaced apart from the first location such that current flows through the phase-change layer from the first location to the second location. The outer electrode contact arm has a lowermost surface that is coplanar with the lowermost surface of the phase-change layer.

Abstract: Embodiments disclosed herein include a semiconductor structure. The semiconductor structure may include an NFET transistor with NFET nanosheets and a first workfunction setting metal that is pinched off within spaces between the NFET nanosheets and a PFET transistor with PFET nanosheets surrounded by a thin layer of a second workfunction setting metal. The semiconductor structure may also include a doped metal between the PFET nanosheets surrounded by a thin layer of a workfunction setting metal.

Abstract: A method for system authentication includes subjecting a system to a challenge. The method further includes receiving a response from the system. The received response is dependent upon a location of a filament in a resistive random-access memory device of the system. Additionally, the response is also a unique identifier.

Abstract: A phase-change memory cell includes an insulating layer; a first electrode embedded in the insulating layer, wherein an outer end of the first electrode is locally flush with an outer surface of the insulating layer; a second electrode, larger than the first electrode, and spaced from the first electrode; a compositionally homogenous crystalline phase change material layer; and a highly oriented seed layer. A crystal structure of the homogenous phase change material layer is correlated with a crystal structure of the highly oriented seed layer. The compositionally homogenous phase change material layer and the highly oriented seed layer are located at least partially between the first and second electrodes.

Abstract: A security key associated with a plurality of programmable switches included in an integrated circuit is received. The plurality of programmable switches are set causing the plurality of programmable switches to be conductive. Reset pulses are applied to a first set of programmable switches included in the plurality of programmable switches based on the received security key.

Abstract: A tunable nonvolatile resistive element, wherein the device conductance is modulated by changing the length of a contact between a phase change material and a resistive liner. By choosing the contact length to be less than the transfer length a linear modulation of the conductance is obtained.