Abstract: Nanoscale efuses, antifuses, and planar coil inductors are disclosed. A copper damascene process can be used to make all of these circuit elements. A low-temperature copper etch process can be used to make the efuses and efuse-like inductors. The circuit elements can be designed and constructed in a modular fashion by linking a matrix of metal columns in different configurations and sizes. The number of metal columns, or the size of a dielectric mesh included in the circuit element, determines its electrical characteristics. Alternatively, the efuses and inductors can be formed from interstitial metal that is either deposited into a matrix of dielectric columns, or left behind after etching columnar openings in a block of metal. Arrays of metal columns also serve a second function as features that can improve polish uniformity in place of conventional dummy structures. Use of such modular arrays provides flexibility to integrated circuit designers.

Abstract: A drying apparatus for drying a semiconductor wafer includes a processing chamber including a rinsing section and a drying section adjacent thereto. The rinsing section has a chamber loading slot associated therewith for receiving the semiconductor wafer. The drying section has a chamber unloading slot associated therewith for outputting the semiconductor wafer. An exhaust control cap is carried by the processing chamber and includes a bottom wall, a top wall, at least one intermediate wall between the bottom and top walls, and a side wall coupled to the top, bottom and the at least one intermediate wall to define stacked exhaust sections. The exhaust control cap has a cap loading slot aligned with the chamber loading slot, a cap unloading slot aligned with the chamber unloading slot, and at least one exhaust port configured to be coupled to a vacuum source.

Abstract: A method and apparatus for irradiation therapy using voxel based function measurements of organs-at-risk (OAR). The method includes determining size and location of each voxel of a plurality of voxels in a reference frame of a radiation device. The method further includes obtaining measurements that relate to utility of tissue type at each voxel. The method further includes determining a subset of the voxels that enclose an organ-at-risk (OAR) volume. The method further includes determining a value of a utility measure fj at each voxel of the subset based on a corresponding value of the measurements. The method further includes determining a series of beam shapes and intensities which minimize a value of an objective function that is based on a computed dose delivered to an OAR voxel multiplied by the utility measure fj for that voxel summed over all voxels.

Abstract: An integrated circuit die includes a silicon substrate. PMOS and NMOS transistors are formed on the silicon substrate. The carrier mobilities of the PMOS and NMOS transistors are increased by introducing tensile stress to the channel region of the NMOS transistors and compressive stress to the channel regions of the PMOS transistors. Tensile stress is introduced by including a region of SiGe below the channel region of the NMOS transistors. Compressive stress is introduced by including regions of SiGe in the source and drain regions of the PMOS transistors.

Abstract: Nanoscale efuses, antifuses, and planar coil inductors are disclosed. A copper damascene process can be used to make all of these circuit elements. A low-temperature copper etch process can be used to make the efuses and efuse-like inductors. The circuit elements can be designed and constructed in a modular fashion by linking a matrix of metal columns in different configurations and sizes. The number of metal columns, or the size of a dielectric mesh included in the circuit element, determines its electrical characteristics. Alternatively, the efuses and inductors can be formed from interstitial metal that is either deposited into a matrix of dielectric columns, or left behind after etching columnar openings in a block of metal. Arrays of metal columns also serve a second function as features that can improve polish uniformity in place of conventional dummy structures. Use of such modular arrays provides flexibility to integrated circuit designers.

Abstract: Provided are techniques for populating a new text index. In response to determining that a limit for indexing a set of documents to the new text index has been reached, a commit is performed, a restart key is updated to identify a next document to be indexed, and the next document is indexed in a next commit cycle.

Abstract: Provided are techniques for populating a new text index. In response to determining that a limit for indexing a set of documents to the new text index has been reached, a commit is performed, a restart key is updated to identify a next document to be indexed, and the next document is indexed in a next commit cycle.

Abstract: A support structure includes an internal cavity. An elastic membrane extends to divide the internal cavity into a first chamber and a second chamber. The elastic membrane includes a nanometric-sized pin hole extending there through to interconnect the first chamber to the second chamber. The elastic membrane is formed of a first electrode film and a second electrode film separated by a piezo insulating film. Electrical connection leads are provided to support application of a bias current to the first and second electrode films of the elastic membrane. In response to an applied bias current, the elastic membrane deforms by bending in a direction towards one of the first and second chambers so as to produce an increase in a diameter of the pin hole.

Abstract: Ultra-low-k dielectric materials used as inter-layer dielectrics in high-performance integrated circuits are prone to be structurally unstable. The Young's modulus of such materials is decreased, resulting in porosity, poor film strength, cracking, and voids. An alternative dual damascene interconnect structure incorporates deep air gaps into a high modulus dielectric material to maintain structural stability while reducing capacitance between adjacent nanowires. Incorporation of a deep air gap having k=1.0 compensates for the use of a higher modulus film having a dielectric constant greater than the typical ultra-low-k (ULK) dielectric value of about 2.2. The higher modulus film containing the deep air gap is used as an insulator and a means of reducing fringe capacitance between adjacent metal lines. The dielectric layer between two adjacent metal lines thus forms a ULK/high-modulus dielectric bi-layer.

Abstract: Irradiation treatment can be used before, during, or after a surgical treatment or other injury to the brain to decrease or prevent subsequent injury. Injury to the brain during surgery can induce the infiltration of peripheral immune cells, including splenic immune cells, into the brain. The infiltration of immune cells can create acute elevations in brain edema and blood-brain barrier disruption thereby decreasing neurological recover and patient outcomes. Irradiation of peripheral immune cells, or the region of the body in which the cells are derived, can allow for inactivation of the cells and prevent infiltration into the surgical site, for example, the brain.

Abstract: Single gate and dual gate FinFET devices suitable for use in an SRAM memory array have respective fins, source regions, and drain regions that are formed from portions of a single, contiguous layer on the semiconductor substrate, so that STI is unnecessary. Pairs of FinFETs can be configured as dependent-gate devices wherein adjacent channels are controlled by a common gate, or as independent-gate devices wherein one channel is controlled by two gates. Metal interconnects coupling a plurality of the FinFET devices are made of a same material as the gate electrodes. Such structural and material commonalities help to reduce costs of manufacturing high-density memory arrays.

Abstract: An interconnect structure for use in coupling transistors in an integrated circuit is disclosed, including various configurations in which ferroelectric capacitors exhibiting negative capacitance are coupled in series with dielectric capacitors. In one embodiment, the negative capacitor includes a dielectric/ferroelectric bi-layer. When a negative capacitor is electrically coupled in series with a conventional dielectric capacitor, the series combination behaves like a stable ferroelectric capacitor for which the overall capacitance can be measured experimentally, and tuned to a desired value. The composite capacitance of a dielectric capacitor and a ferroelectric capacitor having negative capacitance coupled in series is, in theory, infinite, and in practice, very large. A series combination of positive and negative capacitors within a microelectronic interconnect structure can be used to make high capacity DRAM memory cells.

Abstract: An adaptive uniform polishing system is equipped with feedback control to apply localized adjustments during a polishing operation. The adaptive uniform polishing system disclosed has particular application to the semiconductor industry. Such an adaptive uniform polishing system includes a rotatable head that holds a semiconductor wafer, and a processing unit structured to be placed in contact with an exposed surface of the wafer. The processing unit includes a rotatable macro-pad and a plurality of rotatable micro-pads that can polish different portions of the exposed surface at different rotation speeds and pressures. Thus, uniformity across the exposed surface can be enhanced by applying customized treatments to different areas. Customized treatments can include the use of different pad materials and geometries. Parameters of the adaptive uniform polishing system are programmable, based on in-situ data or data from other operations in a fabrication process, using advanced process control.

Abstract: A wavy line interconnect structure that accommodates small metal lines and enlarged diameter vias is disclosed. The enlarged diameter vias can be formed using a self-aligned dual damascene process without the need for a separate via lithography mask. The enlarged diameter vias make direct contact with at least three sides of the underlying metal lines, and can be aligned asymmetrically with respect to the metal line to increase the packing density of the metal pattern. The resulting vias have an aspect ratio that is relatively easy to fill, while the larger via footprint provides low via resistance. An interconnect structure having enlarged diameter vias can also feature air gaps to reduce the chance of dielectric breakdown. By allowing the via footprint to exceed the minimum size of the metal line width, a path is cleared for further process generations to continue shrinking metal lines to dimensions below 10 nm.

Abstract: Stress is introduced into the channel of an SOI FinFET device by transfer directly from a metal gate. In SOI devices in particular, stress transfer efficiency from the metal gate to the channel is nearly 100%. Either tensile or compressive stress can be applied to the fin channel by choosing different materials to be used in the gate stack as the bulk gate material, a gate liner, or a work function material, or by varying processing parameters during deposition of the gate or work function materials. P-gates and N-gates are therefore formed separately. Gate materials suitable for use as stressors include tungsten (W) for NFETs and titanium nitride (TiN) for PFETs. An optical planarization material assists in patterning the stress-inducing metal gates. A simplified process flow is disclosed in which isolation regions are formed without need for a separate mask layer, and gate sidewall spacers are not used.

Abstract: CMP selectivity, removal rate, and uniformity are controlled both locally and globally by altering electric charge at the wafer surface. Surface charge characterization is performed by an on-board metrology module. Based on a charge profile map, the wafer can be treated in an immersion bath to impart a more positive or negative charge overall, or to neutralize the entire wafer before the CMP operation is performed. If charge hot spots are detected on the wafer, a charge pencil can be used to neutralize localized areas. One type of charge pencil bears a tapered porous polymer tip that is placed in close proximity to the wafer surface. Films present on the wafer absorb ions from, or surrender ions to, the charge pencil tip, by electrostatic forces. The charge pencil can be incorporated into a CMP system to provide an in-situ treatment prior to the planarization step or the slurry removal step.

Abstract: A wavy line interconnect structure that accommodates small metal lines and large vias is disclosed. A lithography mask design used to pattern metal line trenches uses optical proximity correction (OPC) techniques to approximate wavy lines using rectangular opaque features. The large vias can be formed using a self-aligned dual damascene process without the need for a separate via lithography mask. Instead, a sacrificial layer allows etching of an underlying thick dielectric block, while protecting narrow features of the trenches that correspond to the metal line interconnects. The resulting vias have an aspect ratio that is relatively easy to fill, while the larger via footprint provides low via resistance. By lifting the shrink constraint for vias, thereby allowing the via footprint to exceed the minimum size of the metal line width, a path is cleared for further process generations to continue shrinking metal lines to dimensions below 10 nm.

Abstract: A semiconductor device may include a substrate, and an array of PCM memory cells above the substrate. Each PCM memory cell may include first and second vertically aligned electrodes, a first dielectric layer between the first and second electrodes, a carbon nanotube extending vertically through the first dielectric layer from the second electrode and toward the first electrode, and a PCM body between the first electrode and the at least one carbon nanotube.

Abstract: The present invention relates to methods and pharmaceutical compositions for treating obesity or obesity-related disorders in a subject suffering from or predisposed to developing obesity or an obesity-related disorder, or for inhibiting the infectivity of HIV, by administering oleuropein, an analogue or derivative thereof, or the major metabolites of oleuropein including oleuropein aglycone, hydroxytyrosol, and elenolic acid or their analogues, or derivatives thereof, an iridoid glycoside, or a secoiridoid glycoside or analogues or derivatives thereof, or any combination of the foregoing including olive leave extract. The invention also relates to methods for screening/diagnosing a subject having, or predisposed to having obesity or a related disorder by measuring the expression profiles of an adipogenic gene selected from PPAR?2, LPL and ?P2 gene and gene product, or other adipogenic, lipogenic, or lipolytic genes and gene products in an individual.

Abstract: Integrated circuit devices and fabrication techniques. A semiconductor device fabrication method may include doping, in a same processing step, first and second portions of a substrate of an integrated circuit. The first portion corresponds to a doped region of a semiconductor device. The second portion corresponds to a via contact. The method may further include, after the doping, forming the gate of the semiconductor device.