Patents by Inventor Habib Hichri
Habib Hichri has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20120153474Abstract: A method of manufacturing an integrated circuit system includes: providing a substrate; forming a polysilicon layer over the substrate; forming an anti-reflective coating layer over the polysilicon layer; etching an anti-reflective coating pattern into the anti-reflective coating layer leaving an anti-reflective coating residue over the polysilicon layer; and etching the anti-reflective coating residue with an etchant gas mixture comprising hydrogen bromide, chlorine, and oxygen to remove the anti-reflective coating residue for mitigating the formation of a polysilicon protrusion.Type: ApplicationFiled: December 21, 2010Publication date: June 21, 2012Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Xiang Hu, Helen Wang, Arifuzzaman (Arif) Sheikh, Habib Hichri, Richard Wise
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Patent number: 8168451Abstract: Inspection methods. A method includes adhering an optical blocking layer directly onto and in direct mechanical contact with a semiconductor process wafer, the blocking layer being substantially opaque to a range of wavelengths of light; applying at least one layer over the blocking layer; and inspecting optically at least one wavelength at least one inspection area, the blocking layer extending substantially throughout the inspection area. An inspection method including adhering an optical absorbing layer to a semiconductor process wafer, where the absorbing layer is configured to substantially absorb a range of wavelengths of light; applying at least one layer over the absorbing layer; and inspecting optically at least one wavelength at least one inspection area of the process wafer. A manufacturing method including ascertaining if a defect is present within a photoresist layer, and changing a semiconductor manufacturing process to prevent the defect, if the defect is present.Type: GrantFiled: December 30, 2009Date of Patent: May 1, 2012Assignee: International Business Machines CorporationInventors: Colin J. Brodsky, Mary Jane Brodsky, Sean Burns, Habib Hichri
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Patent number: 8030157Abstract: A method of forming a trench in a semiconductor device formed of a substrate and a first layer formed over the substrate includes forming an initial trench that passes through the first layer to the substrate, the initial trench having a diameter that decreases from a first diameter to a second diameter, the second diameter being measured at a distance closer to the substrate than the first diameter; exposing the trench to a dopant via an orthogonal ion implant to form doped regions sidewalls of the trench; and etching the trench to remove at least some of the doped regions.Type: GrantFiled: May 18, 2010Date of Patent: October 4, 2011Assignee: International Business Machines CorporationInventors: Habib Hichri, Ahmad D. Katnani, Kaushik A. Kumar, Narender Rana, Richard S. Wise, Hakeem B. S. Akinmade-Yusuff
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Publication number: 20100112730Abstract: Inspection methods. A method includes adhering an optical blocking layer directly onto and in direct mechanical contact with a semiconductor process wafer, the blocking layer being substantially opaque to a range of wavelengths of light; applying at least one layer over the blocking layer; and inspecting optically at least one wavelength at least one inspection area, the blocking layer extending substantially throughout the inspection area. An inspection method including adhering an optical absorbing layer to a semiconductor process wafer, where the absorbing layer is configured to substantially absorb a range of wavelengths of light; applying at least one layer over the absorbing layer; and inspecting optically at least one wavelength at least one inspection area of the process wafer. A manufacturing method including ascertaining if a defect is present within a photoresist layer, and changing a semiconductor manufacturing process to prevent the defect, if the defect is present.Type: ApplicationFiled: December 30, 2009Publication date: May 6, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Colin Brodsky, Mary Jane Brodsky, Sean Burns, Habib Hichri
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Patent number: 7645621Abstract: Inspection methods. A method includes adhering an optical blocking layer directly onto and in direct mechanical contact with a semiconductor process wafer, the blocking layer being substantially opaque to a range of wavelengths of light; applying at least one layer over the blocking layer; and inspecting optically at least one wavelength at least one inspection area, the blocking layer extending substantially throughout the inspection area. An inspection method including adhering an optical absorbing layer to a semiconductor process wafer, where the absorbing layer is configured to substantially absorb a range of wavelengths of light; applying at least one layer over the absorbing layer; and inspecting optically at least one wavelength at least one inspection area of the process wafer. A manufacturing method including ascertaining if a defect is present within a photoresist layer, and changing a semiconductor manufacturing process to prevent the defect, if the defect is present.Type: GrantFiled: October 16, 2007Date of Patent: January 12, 2010Assignee: International Business Machines CorporationInventors: Colin Brodsky, Mary Jane Brodsky, Sean Burns, Habib Hichri
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Publication number: 20090176350Abstract: A method embodiment deposits a first dielectric layer over a transistor and then implants a gettering agent into the first dielectric layer. After this first dielectric layer is formed, the method forms a second (thicker) dielectric layer over the first dielectric layer. After this, the standard contacts are formed through the insulating layer to the source, drain, gate, etc. of the transistor. Additionally, reactive ion etching, chemical mechanical processing, and other back-end-of-line processing are performed. The back-end-of-line processes can introduce mobile ions into the dielectric over a transistor; however, the gettering agent traps the mobile ions and prevents the mobile ions from contaminating the transistor.Type: ApplicationFiled: January 4, 2008Publication date: July 9, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: MICHAEL P. BELYANSKY, Brian J. Greene, Habib Hichri, Tai-Chi Su
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Patent number: 7544609Abstract: A method for integrating cap liner formation in back-end-of-line (BEOL) processing of a semiconductor device includes forming a trench structure within an insulating layer of the semiconductor device, depositing a first liner material over a top surface of the insulating layer, including sidewall and bottom surfaces of the trench, and partially filling the trench with a wiring metal material to a height corresponding to a final intended line height. A second liner material is over the wiring metal material, and a sacrificial fill material is formed over the second liner material. The sacrificial fill is planarized down to the level of the second liner material over the wiring metal material partially filling the trench, wherein a remaining portion of the second liner material defines a cap liner of the wiring metal.Type: GrantFiled: February 9, 2007Date of Patent: June 9, 2009Assignee: International Business Machines CorporationInventors: Matthew S. Angyal, Habib Hichri, Christopher J. Penny, David K. Watts
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Publication number: 20090117360Abstract: A non-photosensitive polymeric resist containing at least two immiscible polymeric block components is deposited on the planar surface. The non-photosensitive polymeric resist is annealed to allow phase separation of immiscible components and developed to remove at least one of the at least two polymeric block components. Nanoscale features, i.e., features of nanometer scale, including at least one recessed region having a nanoscale dimension is formed in the polymeric resist. The top surface of the polymeric resist is modified for enhanced etch resistance by an exposure to an energetic beam, which allows the top surface of the patterned polymeric resist to become more resistant to etching processes and chemistries. The enhanced ratio of etch resistance between the two types of surfaces provides improved image contrast and fidelity between areas having the top surface and the at least one recessed region.Type: ApplicationFiled: November 1, 2007Publication date: May 7, 2009Applicant: International Business Machines CorporationInventors: Lawrence A. Clevenger, Timothy J. Dalton, Habib Hichri, Louis L. Hsu, Kaushik A. Kumar, Carl Radens, Shahab Siddiqui, Chih-Chao Yang
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Publication number: 20090097017Abstract: Inspection methods. A method includes adhering an optical blocking layer directly onto and in direct mechanical contact with a semiconductor process wafer, the blocking layer being substantially opaque to a range of wavelengths of light; applying at least one layer over the blocking layer; and inspecting optically at least one wavelength at least one inspection area, the blocking layer extending substantially throughout the inspection area. An inspection method including adhering an optical absorbing layer to a semiconductor process wafer, where the absorbing layer is configured to substantially absorb a range of wavelengths of light; applying at least one layer over the absorbing layer; and inspecting optically at least one wavelength at least one inspection area of the process wafer. A manufacturing method including ascertaining if a defect is present within a photoresist layer, and changing a semiconductor manufacturing process to prevent the defect, if the defect is present.Type: ApplicationFiled: October 16, 2007Publication date: April 16, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Colin Brodsky, Mary Jane Brodsky, Sean Burns, Habib Hichri
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Publication number: 20090026587Abstract: A dielectric layer for a semiconductor device having a low overall dielectric constant, good adhesion to the semiconductor substrate, and good resistance to cracking due to thermal cycling. The dielectric layer is made by a process involving continuous variation of dielectric material deposition conditions to provide a dielectric layer having a gradient of dielectric constant.Type: ApplicationFiled: January 14, 2004Publication date: January 29, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Matthew Angyal, Habib Hichri, Henry A. Nye, III, Dale McHerron, Jia Lee
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Patent number: 7475368Abstract: A system, a method and a computer program product for analyzing a circuit design provide for discretizing the circuit design into a series of pixels. A fraction of at least one constituent material is determined for each pixel. A deflection is also determined for each pixel. The deflection is predicated upon a planarizing of the pixel, and it is calculated while utilizing an algorithm that includes the fraction of the at least one constituent material. A series of deflections for the series of pixels may be mapped and evaluated.Type: GrantFiled: January 20, 2006Date of Patent: January 6, 2009Assignee: International Business Machines CorporationInventors: Matthew S. Angyal, Giovanni Fiorenza, Habib Hichri, Andrew Lu, Dale C. McHerron, Conal E. Murray
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Patent number: 7456098Abstract: Stacked via pillars, such as metal via pillars, are provided at different and designated locations in IC chips to support the chip structure during processing and any related processing stresses such as thermal and mechanical stresses. These stacked via pillars connect and extend from a base substrate of the strip to a top oxide cap of the chip. The primary purpose of the stacked via pillars is to hold the chip structure together to accommodate any radial deformations and also to relieve any stress, thermal and/or mechanical, build-tip during processing or reliability testing. The stacked via pillars are generally not electrically connected to any active lines or vias, however in some embodiments the stacked via pillars can provide an additional function of providing an electrical connection in the chip.Type: GrantFiled: April 13, 2006Date of Patent: November 25, 2008Assignee: International Business Machines CorporationInventors: Habib Hichri, Xiao H. Liu, Vincent J. McGahay, Conal E. Murray, Jawahar P. Nayak, Thomas M. Shaw
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Publication number: 20080194099Abstract: A method for integrating cap liner formation in back-end-of-line (BEOL) processing of a semiconductor device includes forming a trench structure within an insulating layer of the semiconductor device, depositing a first liner material over a top surface of the insulating layer, including sidewall and bottom surfaces of the trench, and partially filling the trench with a wiring metal material to a height corresponding to a final intended line height. A second liner material is over the wiring metal material, and a sacrificial fill material is formed over the second liner material. The sacrificial fill is planarized down to the level of the second liner material over the wiring metal material partially filling the trench, wherein a remaining portion of the second liner material defines a cap liner of the wiring metal.Type: ApplicationFiled: February 9, 2007Publication date: August 14, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Matthew S. Angyal, Habib Hichri, Christopher J. Penny, David K. Watts
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Publication number: 20070273004Abstract: The invention forms integrated circuit devices of similar structure and dissimilar depth, such as interconnects and inductors, simultaneously. The invention deposits a conformal polymer over an area on a substrate with vias and an area without vias. Simultaneously, cavities are formed in the areas with and without vias. The depth of the cavities formed in the areas with vias will extend deeper into the substrate than the cavities formed in areas without vias. Such occurs because the polymer deposits unevenly along the surface of the substrate and more specifically, more thinly in areas with underlying depressions. Once filled with a conductive material, cavities which extend more deeply into the substrate, which were formed in areas with vias, become inductors, and the cavities which extend less deeply into the substrate, which were formed in areas without vias, become interconnects.Type: ApplicationFiled: August 9, 2007Publication date: November 29, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Habib Hichri, Kimberly Larsen, Helen Maynard, Kevin Petrarca
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Patent number: 7279426Abstract: The invention forms integrated circuit devices of similar structure and dissimilar depth, such as interconnects and inductors, simultaneously. The invention deposits a conformal polymer over an area on a substrate with vias and an area without vias. Simultaneously, cavities are formed in the areas with and without vias. The depth of the cavities formed in the areas with vias will extend deeper into the substrate than the cavities formed in areas without vias. Such occurs because the polymer deposits unevenly along the surface of the substrate and more specifically, more thinly in areas with underlying depressions. Once filled with a conductive material, cavities which extend more deeply into the substrate, which were formed in areas with vias, become inductors, and the cavities which extend less deeply into the substrate, which were formed in areas without vias, become interconnects.Type: GrantFiled: September 22, 2005Date of Patent: October 9, 2007Assignee: International Business Machines CorporationInventors: Habib Hichri, Kimberly A. Larsen, Helen L. Maynard, Kevin S. Petrarca
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Patent number: 7253100Abstract: Methods are disclosed for reducing damage to an ultra-low dielectric constant (ULK) dielectric during removal of a planarizing layer such as a crosslinked polymer. The methods at least partially fill an opening with an at most lightly crosslinked polymer, followed by the planarizing layer. When the at most lightly crosslinked polymer and planarizing layer are removed, the at most lightly crosslinked polymer removal is easier than removal of the planarizing layer, i.e., crosslinked polymer, and does not damage the surrounding dielectric compared to removal chemistries used for the crosslinked polymer.Type: GrantFiled: November 17, 2005Date of Patent: August 7, 2007Assignee: International Business Machines CorporationInventors: Ronald A. DellaGuardia, Daniel C. Edelstein, Habib Hichri, Vincent J. McGahay
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Publication number: 20070174796Abstract: A system, a method and a computer program product for analyzing a circuit design provide for discretizing the circuit design into a series of pixels. A fraction of at least one constituent material is determined for each pixel. A deflection is also determined for each pixel. The deflection is predicated upon a planarizing of the pixel, and it is calculated while utilizing an algorithm that includes the fraction of the at least one constituent material. A series of deflections for the series of pixels may be mapped and evaluated.Type: ApplicationFiled: January 20, 2006Publication date: July 26, 2007Applicant: International Business Machines CorporationInventors: Matthew Angyal, Giovanni Fiorenza, Habib Hichri, Andrew Lu, Dale McHerron, Conal Murray
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Publication number: 20070111466Abstract: Methods are disclosed for reducing damage to an ultra-low dielectric constant (ULK) dielectric during removal of a planarizing layer such as a crosslinked polymer. The methods at least partially fill an opening with an at most lightly crosslinked polymer, followed by the planarizing layer. When the at most lightly crosslinked polymer and planarizing layer are removed, the at most lightly crosslinked polymer removal is easier than removal of the planarizing layer, i.e., crosslinked polymer, and does not damage the surrounding dielectric compared to removal chemistries used for the crosslinked polymer.Type: ApplicationFiled: November 17, 2005Publication date: May 17, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ronald DellaGuardia, Daniel Edelstein, Habib Hichri, Vincent McGahay
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Patent number: 7214608Abstract: Methods for sealing an organic ILD layer and a metal layer after an etching step. The method includes etching through an ILD layer and leaving a remaining portion of an underlying metal layer cap, maintaining the device in an inert gas, and depositing at least a portion of a liner into the opening to seal the ILD layer and the metal layer. Subsequent processing may include formation of a via by etching through the portion of the liner and the remaining portion of the cap layer, and depositing a metal.Type: GrantFiled: July 29, 2004Date of Patent: May 8, 2007Assignee: International Business Machines CorporationInventors: Matthew S. Angyal, Peter E. Biolsi, Lawrence A. Clevenger, Habib Hichri, Bernd E. Kastenmeier, Michael W. Lane, Jeffrey R. Marino, Vincent J. McGahay, Theodorus E. Standaert
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Publication number: 20070066073Abstract: The invention forms integrated circuit devices of similar structure and dissimilar depth, such as interconnects and inductors, simultaneously. The invention deposits a conformal polymer over an area on a substrate with vias and an area without vias. Simultaneously, cavities are formed in the areas with and without vias. The depth of the cavities formed in the areas with vias will extend deeper into the substrate than the cavities formed in areas without vias. Such occurs because the polymer deposits unevenly along the surface of the substrate and more specifically, more thinly in areas with underlying depressions. Once filled with a conductive material, cavities which extend more deeply into the substrate, which were formed in areas with vias, become inductors, and the cavities which extend less deeply into the substrate, which were formed in areas without vias, become interconnects.Type: ApplicationFiled: September 22, 2005Publication date: March 22, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Habib Hichri, Kimberly Larsen, Helen Maynard, Kevin Petrarca