Abstract: A system and method for detecting a loss of plasma confinement. The system includes a plasma chamber that includes a plasma space and a non-plasma space. A plasma apparatus generates a plasma within the plasma space. The non-plasma space surrounds the plasma space and is separated from the plasma space by a confinement barrier that is adapted to confine the plasma in the plasma space during performance of an operational process by the plasma on a substrate disposed within the plasma space. Plasma detectors distributed on bounding surfaces of the non-plasma space are adapted to detect plasma that has escaped from the plasma space during performance of the operational process. The operational process is performed while the plasma detectors are monitoring the non-plasma space for a presence of the escaped plasma in the non-plasma space. If the monitoring has detected the escaped plasma, then the operational process is aborted.

Abstract: An advanced back-end-of-line (BEOL) interconnect structure having a hybrid dielectric is disclosed. The inter-layer dielectric (ILD) for the via level is preferably different from the ILD for the line level. In a preferred embodiment, the via-level ILD is formed of a low-k SiCOH material, and the line-level ILD is formed of a low-k polymeric thermoset material.

Abstract: Stacked via pillars, such as metal via pillars, are provided at different and designated locations in IC chips to support the chip structure during processing and any related processing stresses such as thermal and mechanical stresses. These stacked via pillars connect and extend from a base substrate of the strip to a top oxide cap of the chip. The primary purpose of the stacked via pillars is to hold the chip structure together to accommodate any radial deformations and also to relieve any stress, thermal and/or mechanical, build-tip during processing or reliability testing. The stacked via pillars are generally not electrically connected to any active lines or vias, however in some embodiments the stacked via pillars can provide an additional function of providing an electrical connection in the chip.

Abstract: Stacked via pillars, such as metal via pillars, are provided at different and designated locations in IC chips to support the chip structure during processing and any related processing stresses such as thermal and mechanical stresses. These stacked via pillars connect and extend from a base substrate of the strip to a top oxide cap of the chip. The primary purpose of the stacked via pillars is to hold the chip structure together to accommodate any radial deformations and also to relieve any stress, thermal and/or mechanical, build-up during processing or reliability testing. The stacked via pillars are generally not electrically connected to any active lines or vias, however in some embodiments the stacked via pillars can provide an additional function of providing an electrical connection in the chip.

Abstract: An interlevel dielectric layer (ILD) comprises a low-k dielectric layer; and a low-k dielectric film, deposited under compressive stress, atop the dielectric layer. The dielectric layer comprises a low-k material, such as an organosilicon glass (OSG) or a SiCOH material. The dielectric film has a thickness, which is 2%–10% of the thickness of the dielectric layer, has a similar chemical composition to the dielectric layer, but has a different morphology than the dielectric layer. The dielectric film is deposited under compressive stress, in situ, at or near the end of the dielectric layer deposition by altering a process that was used to deposit the low-k dielectric layer.

Abstract: Methods for sealing an organic ILD layer and a metal layer after an etching step. The method includes etching through an ILD layer and leaving a remaining portion of an underlying metal layer cap, maintaining the device in an inert gas, and depositing at least a portion of a liner into the opening to seal the ILD layer and the metal layer. Subsequent processing may include formation of a via by etching through the portion of the liner and the remaining portion of the cap layer, and depositing a metal.

Abstract: An interlevel dielectric layer (ILD) comprises a low-k dielectric layer; and a low-k dielectric film, deposited under compressive stress, atop the dielectric layer. The dielectric layer comprises a low-k material, such as an organosilicon glass (OSG) or a SiCOH material. The dielectric film has a thickness, which is 2%-10% of the thickness of the dielectric layer, has a similar chemical composition to the dielectric layer, but has a different morphology than the dielectric layer. The dielectric film is deposited under compressive stress, in situ, at or near the end of the dielectric layer deposition by altering a process that was used to deposit the low-k dielectric layer.

Abstract: An advanced back-end-of-line (BEOL) interconnect structure having a hybrid dielectric is disclosed. The inter-layer dielectric (ILD) for the via level is preferably different from the ILD for the line level. In a preferred embodiment, the via-level ILD is formed of a low-k SiCOH material, and the line-level ILD is formed of a low-k polymeric thermoset material.

Abstract: Stacked via pillars, such as metal via pillars, are provided at different and designated locations in IC chips to support the chip structure during processing and any related processing stresses such as thermal and mechanical stresses. These stacked via pillars connect and extend from a base substrate of the strip to a top oxide cap of the chip. The primary purpose of the stacked via pillars is to hold the chip structure together to accommodate any radial deformations and also to relieve any stress, thermal and/or mechanical, build-up during processing or reliability testing. The stacked via pillars are generally not electrically connected to any active lines or vias, however in some embodiments the stacked via pillars can provide an additional function of providing an electrical connection in the chip.

Abstract: A process of removing impurities from a cured low dielectric constant organic polymeric film disposed on a semiconductor device. The process involves disposing a low dielectric constant curable organic polymeric film on an electrically conductive surface of a semiconductor device. The organic polymeric film is cured on the semiconductor device and thereupon contacted with supercritical carbon dioxide, optionally in the presence of at least one cosolvent.

Abstract: An advanced back-end-of-line (BEOL) interconnect structure having a hybrid dielectric is disclosed. The inter-layer dielectric (ILD) for the via level is preferably different from the ILD for the line level. In a preferred embodiment, the via-level ILD is formed of a low-k SiCOH material, and the line-level ILD is formed of a low-k polymeric thermoset material.

Abstract: A semiconductor wafer provided with a thermosetting porous insulating film, wherein the insulating film is made porous, cured and polymerized on the wafer. The film is characterized by a very low dielectric constant based on its constituency and porosity, the latter property of which is caused by the inclusion of liquid or supercritical carbon dioxide in the polymeric reaction mixture.

Abstract: An interconnect structure for a semiconductor device includes an organic, low dielectric constant (low-k) dielectric layer formed over a lower metallization level. A via formed is within the low-k dielectric layer, the via connecting a lower metallization line formed in the lower metallization level with an upper metallization line formed in an upper metallization level. The via is surrounded by a structural collar selected from a material having a coefficient of thermal expansion (CTE) so as to protect the via from shearing forces following a thermal expansion of the low-k dielectric layer.

Abstract: A semiconductor wafer provided with a thermosetting porous insulating film, wherein the insulating film is made porous, cured and polymerized on the wafer. The film is characterized by a very low dielectric constant based on its constituency and porosity, the latter property of which is caused by the inclusion of liquid or supercritical carbon dioxide in the polymeric reaction mixture.

Abstract: An interconnect structure for a semiconductor device includes an organic, low dielectric constant (low-k) dielectric layer formed over a lower metallization level. A via formed is within the low-k dielectric layer, the via connecting a lower metallization line formed in the lower metallization level with an upper metallization line formed in an upper metallization level. The via is surrounded by a structural collar selected from a material having a coefficient of thermal expansion (CTE) so as to protect the via from shearing forces following a thermal expansion of the low-k dielectric layer.

Abstract: An advanced back-end-of-line (BEOL) interconnect structure having a hybrid dielectric is disclosed. The inter-layer dielectric (ILD) for the via level is preferably different from the ILD for the line level. In a preferred embodiment, the via-level ILD is formed of a low-k SiCOH material, and the line-level ILD is formed of a low-k polymeric thermoset material.

Abstract: A semiconductor wafer provided with a thermosetting porous insulating film, wherein the insulating film is made porous, cured and polymerized on the wafer. The film is characterized by a very low dielectric constant based on its constituency and porosity, the latter property of which is caused by the inclusion of liquid or supercritical carbon dioxide in the polymeric reaction mixture.

Abstract: Disclosed is a solution that comprises (A) a solvent; (B) about 0.001 to about 20 wt % of a terpolymer that comprises the condensation reaction product of (1) an aromatic compound that contains a benzene or naphthalene ring substituted with the group OR or SR, where R is hydrogen, alkyl from C1 to C15, or aryl, alkaryl, or aralkyl from C6 to C15; (2) about 0.1 to about 10 moles of a carbonyl compound per mole of said aromatic compound; and (3) about 0.1 to about 10 moles of a thiourea per mole of said aromatic compound (C) about 1 to about 5 wt % of a base; (D) about 0.1 wt % to saturation of a salt; and (E) 0 to about 20 wt % of an alcohol. Also disclosed is a method of making the terpolymer in the absence of an acid catalyst and a method of inhibiting the formation of scale on reactor components in contact with polymerizing vinyl chloride monomer.

Abstract: Disclosed is a solution that comprises

Abstract: Disclosed is a method of polymerizing vinyl chloride or vinylidene chloride monomer. A mixture is prepared of (1) a monomer selected from the group consisting of vinyl chloride, vinylidene chloride, and mixtures thereof with up to about 20 wt % of a comonomer, (2) supercritical carbon dioxide, subcritical carbon dioxide, or liquid carbon dioxide in a weight ratio to the monomer of about 0.5 to about 5; and (3) about 0.1 to about 1 phr of a free radical initiator that is soluble in said supercritical carbon dioxide or a solution of said a free radical initiator in a solvent that is miscible with the carbon dioxide. The mixture is heated to a temperature of about 40 to about 70° C. to polymerize the monomer.