Patents by Inventor Hae-In JUNG

Hae-In JUNG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180122898
    Abstract: A semiconductor device may include: a substrate having first and second surfaces; an interlayer dielectric layer having a first opening to expose the first surface; a first plug positioned in the first opening and isolated from a sidewall of the first opening by a pair of gaps; a bit line extended in any one direction while covering the first plug; a second plug including a lower part adjacent to the first plug and an upper part adjacent to the bit line, and connected to the second surface; a first air gap positioned between the first plug and the lower part of the second plug; and a second air gap positioned between the bit line and the upper part of the second plug, and having a larger width than the first air gap.
    Type: Application
    Filed: November 1, 2017
    Publication date: May 3, 2018
    Inventors: Hae-Jung PARK, Jung-Taik CHEONG, Tae-Woo JUNG, Yun-Je CHOI
  • Patent number: 9941476
    Abstract: The present disclosure provides an organic semiconductor compound, which has superior charge mobility, low band gap, wide light absorption area and adequate molecular energy level. The conductive organic semiconductor compound of the present disclosure can be used as a material for various organic optoelectric devices such as an organic photodiode (OPD), an organic light-emitting diode (OLED), an organic thin-film transistor (OTFT), an organic solar cell, etc. In addition, it can be prepared into a thin film via a solution process, can be advantageously used to fabricate large-area devices and can reduce the cost of device fabrication.
    Type: Grant
    Filed: March 17, 2015
    Date of Patent: April 10, 2018
    Assignee: KOREA INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Hae Jung Son, Min Jae Ko, Bong Soo Kim, Doh-Kwon Lee, Jin Young Kim, Hong Gon Kim, Sungmin Park
  • Patent number: 9930107
    Abstract: Provided is a method for balancing load of a server in a communication system. The method includes receiving, by a client, a new access request message; checking load status of servers that the client itself manages; selecting a lowest-load server among the servers as a server to which the client is to send the new access request message; and sending the new access request message to the selected server.
    Type: Grant
    Filed: November 26, 2012
    Date of Patent: March 27, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hae-Jung Lim, Hong-Seok Yang, Jai-Jin Lim
  • Patent number: 9846324
    Abstract: A display device and a method for fabricating the display device are provided. The display device includes a transparent circuit substrate for use as a touch screen, the transparent circuit substrate includes a transparent substrate, a Polymer Dispersed Liquid Crystal (PDLC) coating layer formed on the transparent substrate, an electrode layer provided on the PDLC coating layer, for applying current to the PDLC coating layer, and an insulation layer provided on the electrode layer.
    Type: Grant
    Filed: June 18, 2014
    Date of Patent: December 19, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Hae-Jung Yang
  • Patent number: 9837490
    Abstract: A semiconductor device may include: a substrate having first and second surfaces; an interlayer dielectric layer having a first opening to expose the first surface; a first plug positioned in the first opening and isolated from a sidewall of the first opening by a pair of gaps; a bit line extended in any one direction while covering the first plug; a second plug including a lower part adjacent to the first plug and an upper part adjacent to the bit line, and connected to the second surface; a first air gap positioned between the first plug and the lower part of the second plug; and a second air gap positioned between the bit line and the upper part of the second plug, and having a larger width than the first air gap.
    Type: Grant
    Filed: January 13, 2016
    Date of Patent: December 5, 2017
    Assignee: SK Hynix Inc.
    Inventors: Hae-Jung Park, Jung-Taik Cheong, Tae-Woo Jung, Yun-Je Choi
  • Patent number: 9825047
    Abstract: A non-volatile memory device according to an aspect of the present disclosure includes a substrate, a plurality of word lines stacked over the substrate and having a stepwise pattern, wherein the plurality of word lines each have a pad region, and a plurality of contact plugs coupled to the respective pad regions of the word lines, wherein a width of a pad region of a first one of the plurality of word lines is greater than a width of a pad region of a second word line lower than the first word line.
    Type: Grant
    Filed: August 16, 2012
    Date of Patent: November 21, 2017
    Assignee: SK Hynix Inc.
    Inventors: Sung Yoon Cho, Hae Jung Lee, Byung Soo Park, Eun Mi Kim
  • Publication number: 20170288159
    Abstract: Disclosed is an electron transport layer for a flexible perovskite solar cell. The electron transport layer includes transition metal-doped titanium dioxide particles. The titanium dioxide particles are densely packed in the electron transport layer. The electron transport layer is transparent. The use of the electron transport layer enables the fabrication of a flexible perovskite solar cell with high power conversion efficiency. Also disclosed is a flexible perovskite solar cell employing the electron transport layer.
    Type: Application
    Filed: January 10, 2017
    Publication date: October 5, 2017
    Inventors: Min Jae KO, Jin JOO, Hae Jung SON, Jai Kyeong KIM, Doh-Kwon LEE, Inyoung JEONG
  • Publication number: 20170288156
    Abstract: An organic solar cell is provided. The organic solar cell includes a photoactive layer in which a low molecular weight conjugated compound as a first organic semiconductor material is mixed with an appropriate amount of a second organic semiconductor material. The first organic semiconductor material includes both electron donors and electron acceptors. The presence of the electron donors and the electron acceptors in the first organic semiconductor material improves the morphology of the photoactive layer, leading to high efficiency of the organic solar cell.
    Type: Application
    Filed: December 14, 2016
    Publication date: October 5, 2017
    Inventors: Hae Jung SON, Min Jae KO, Jai Kyeong KIM, Hyo Sang LEE, Jea Woong JO, Sungmin PARK, JAE HOON YUN
  • Patent number: 9735365
    Abstract: The present disclosure relates to a novel polymer compound and a method for preparing the same. More particularly, the present disclosure relates to a novel conductive low band gap electron donor polymer compound having high photon absorptivity and improved hole mobility, a method for preparing the same and an organic photovoltaic cell containing the same. Since the conductive polymer compound as a low band gap electron donor exhibits high photon absorptivity and superior hole mobility, it can be usefully used as a material for an organic optoelectronic device such as an organic photodiode (OPD), an organic thin-film transistor (OTFT), an organic light-emitting diode (OLED), an organic photovoltaic cell, etc. as well as in the development of a n-type material.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: August 15, 2017
    Assignee: KOREA INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Bong Soo Kim, Hyo Sang Lee, Hong Gon Kim, Min Jae Ko, Doh-Kwon Lee, Jin Young Kim, Hae Jung Son
  • Publication number: 20170155746
    Abstract: A method for manufacturing an electronic device, according to the present disclosure, may include: detecting positions of one or more heat sources, which are disposed in a printed circuit board or in a display of the electronic device, or a path of the heat that is diffused from the heat sources; selecting a heat radiating structure to correspond to the positions of the heat sources or the diffusion path; selecting an adiabatic member or a heat radiating member, which is disposed based the selected heat radiating structure to block or radiate the heat transferred from the heat source; and forming the selected heat radiating structure or disposing the selected adiabatic member or heat radiating member on the periphery of the heat source or on the diffusion path.
    Type: Application
    Filed: October 7, 2016
    Publication date: June 1, 2017
    Inventors: Hae-Jung YANG, Seung-Joo LEE, Kwang-Eun GO, Kang-Sik KIM, Jae-Hoon WOO, Jong-Min LEE
  • Patent number: 9620451
    Abstract: A method includes: forming a first contact hole by etching a first inter-layer dielectric layer; forming a preliminary first conductive plug that fills the first contact hole; forming a bit line structure over the preliminary first conductive plug; forming a first conductive plug by etching the preliminary first conductive plug so that a gap is formed between a sidewall of the first contact hole and the first conductive plug; forming an insulating plug in the gap; forming a multi-layer spacer including a sacrificial spacer; forming a second conductive plug neighboring the bit line structures and the first conductive plugs with the multi-layer spacer and the insulating plug therebetween; and forming a line-type air gap within the multi-layer spacer by removing the sacrificial spacer.
    Type: Grant
    Filed: April 6, 2016
    Date of Patent: April 11, 2017
    Assignee: SK Hynix Inc.
    Inventors: Chang-Youn Hwang, Sang-Kil Kang, Ill-Hee Joe, Dae-Sik Park, Hae-Jung Park, Se-Han Kwon
  • Publication number: 20170005166
    Abstract: A semiconductor device may include: a substrate having first and second surfaces; an interlayer dielectric layer having a first opening to expose the first surface; a first plug positioned in the first opening and isolated from a sidewall of the first opening by a pair of gaps; a bit line extended in any one direction while covering the first plug; a second plug including a lower part adjacent to the first plug and an upper part adjacent to the bit line, and connected to the second surface; a first air gap positioned between the first plug and the lower part of the second plug; and a second air gap positioned between the bit line and the upper part of the second plug, and having a larger width than the first air gap.
    Type: Application
    Filed: January 13, 2016
    Publication date: January 5, 2017
    Inventors: Hae-Jung PARK, Jung-Taik CHEONG, Tae-Woo JUNG, Yun-Je CHOI
  • Patent number: 9514943
    Abstract: A method for etching a gate includes forming a high-k material layer over a substrate; forming an overlying layer over the high-k material layer; performing a first etching process for etching the overlying layer to form an overlying layer pattern; forming a spacer on a sidewall of the overlying layer pattern; and performing a second etching process using plasma including a etch gas and an additive gas, to etch the high-k material layer, wherein an amount of the additive gas is substantially the same as the main etch gas to increase an etch selectivity with respect to the substrate.
    Type: Grant
    Filed: July 26, 2016
    Date of Patent: December 6, 2016
    Assignee: SK Hynix Inc.
    Inventors: Su-Bum Shin, Hae-Jung Lee
  • Publication number: 20160336180
    Abstract: A method for etching a gate includes forming a high-k material layer over a substrate; forming an overlying layer over the high-k material layer; performing a first etching process for etching the overlying layer to form an overlying layer pattern; forming a spacer on a sidewall of the overlying layer pattern; and performing a second etching process using plasma including a etch gas and an additive gas, to etch the high-k material layer, wherein an amount of the additive gas is substantially the same as the main etch gas to increase an etch selectivity with respect to the substrate.
    Type: Application
    Filed: July 26, 2016
    Publication date: November 17, 2016
    Inventors: Su-Bum SHIN, Hae-Jung LEE
  • Patent number: 9484203
    Abstract: In a method of manufacturing a semiconductor device, a gate structure is formed on a substrate. An ion implantation process is performed at an upper portion of the substrate exposed by the gate structure, so that an ion implantation region is formed to have an expanded volume. The ion implantation process uses ions that are identical to a material of the substrate.
    Type: Grant
    Filed: November 7, 2014
    Date of Patent: November 1, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jun-Hee Lim, Ki-Jae Hur, Sung-Hwan Kim, Hae-In Jung, Soo-Jin Hong
  • Publication number: 20160315277
    Abstract: Disclosed is a moisture barrier film for an organic-inorganic hybrid photovoltaic cell which includes an ionic polymer. Also disclosed is an organic-inorganic hybrid photovoltaic cell including the moisture barrier film. The photovoltaic cell has a structure in which the moisture barrier film including an ionic polymer is formed on an absorber layer including an organic-inorganic hybrid perovskite compound. Due to this structure, the moisture barrier film effectively protects the organic-inorganic hybrid perovskite absorber layer, which is very susceptible to moisture, and other constituent layers, from moisture from the external environment so that excellent characteristics of the photovoltaic cell can be maintained for a long time. In other words, the moisture barrier film including an ionic polymer is interposed between the absorber layer and a hole transport layer or between the hole transport layer and a second electrode to enhance the physical and chemical binding therebetween.
    Type: Application
    Filed: February 25, 2016
    Publication date: October 27, 2016
    Inventors: Hae Jung SON, Min Jae KO, Doh-Kwon LEE, Jin Young KIM, Jai Kyeong KIM, Jae Hoon YUN, Hyun Soo CHO, Yujeong KIM
  • Publication number: 20160293872
    Abstract: Disclosed are inorganic nanomaterial-based hydrophobic charge carriers and an organic-inorganic hybrid perovskite solar cell using the charge carriers. In the solar cell, the charge carriers are used as materials for a charge transport layer. The solar cell has high photoelectric efficiency for its price. In addition, the solar cell is prevented from being degraded by moisture. Therefore, the solar cell can be operated stably for a long time despite long-term exposure to a humid environment.
    Type: Application
    Filed: March 29, 2016
    Publication date: October 6, 2016
    Inventors: Min Jae KO, Hae Jung SON, Jin Young KIM, Doh-Kwon LEE, Hee Suk JUNG, Bonkee KOO
  • Patent number: 9431255
    Abstract: A method for etching a gate includes forming a high-k material layer over a substrate; forming an overlying layer over the high-k material layer; performing a first etching process for etching the overlying layer to form an overlying layer pattern; forming a spacer on a sidewall of the overlying layer pattern; and performing a second etching process using plasma including a etch gas and an additive gas, to etch the high-k material layer, wherein an amount of the additive gas is substantially the same as the main etch gas to increase an etch selectivity with respect to the substrate.
    Type: Grant
    Filed: June 12, 2015
    Date of Patent: August 30, 2016
    Assignee: SK Hynix Inc.
    Inventors: Su-Bum Shin, Hae-Jung Lee
  • Publication number: 20160225710
    Abstract: A method includes: forming a first contact hole by etching a first inter-layer dielectric layer; forming a preliminary first conductive plug that fills the first contact hole; forming a bit line structure over the preliminary first conductive plug; forming a first conductive plug by etching the preliminary first conductive plug so that a gap is formed between a sidewall of the first contact hole and the first conductive plug; forming an insulating plug in the gap; forming a multi-layer spacer including a sacrificial spacer; forming a second conductive plug neighboring the bit line structures and the first conductive plugs with the multi-layer spacer and the insulating plug therebetween; and forming a line-type air gap within the multi-layer spacer by removing the sacrificial spacer.
    Type: Application
    Filed: April 6, 2016
    Publication date: August 4, 2016
    Inventors: Chang-Youn HWANG, Sang-Kil KANG, Ill-Hee JOE, Dae-Sik PARK, Hae-Jung PARK, Se-Han KWON
  • Publication number: 20160225999
    Abstract: Provided is an organic-inorganic hybrid photoelectric conversion device including a novel conductive organic semiconductor compound including paracyclophene and an organic-inorganic perovskite compound. A hole transport layer containing the conductive organic semiconductor compound including paracyclophene and a light absorbing layer are bound well organically with each other. Thus, it is possible to accomplish high photoelectric conversion efficiency. In addition, the organic-inorganic hybrid photoelectric conversion device is formed of a solid phase and has high stability, uses inexpensive materials, is obtained by a simple and easy process at low processing cost, and thus allows mass production with high cost efficiency, resulting in high commercial viability.
    Type: Application
    Filed: August 3, 2015
    Publication date: August 4, 2016
    Inventors: Hae Jung SON, Min Jae KO, Hong Gon KIM, Doh-Kwon LEE, Bong Soo KIM, Jin Young KIM, Sungmin PARK, Hyun Soo CHO