Patents by Inventor Hae-In JUNG

Hae-In JUNG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor packages including a heat spreader and methods of forming the same
    Patent number: 9054228
    Abstract: Semiconductor packages including a heat spreader and methods of forming the same are provided. The semiconductor packages may include a first semiconductor chip, a second semiconductor chip, and a heat spreader stacked sequentially. The semiconductor packages may also include a thermal interface material (TIM) layer surrounding the second semiconductor chip and directly contacting a sidewall of the second semiconductor chip. An upper surface of the TIM layer may directly contact a lower surface of the heat spreader, and a sidewall of the TIM layer may be substantially coplanar with a sidewall of the heat spreader. In some embodiments, a sidewall of the first semiconductor chip may be substantially coplanar with the sidewall of the TIM layer.
    Type: Grant
    Filed: January 21, 2014
    Date of Patent: June 9, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eun-Kyoung Choi, Jong-Youn Kim, Sang-Wook Park, Hae-Jung Yu, In-Young Lee, Sang-Uk Han, Ji-Seok Hong
  • Chemical sensor using metal nano-particles and method for manufacturing chemical sensor using metal nano-particles
    Patent number: 9034275
    Abstract: A chemical sensor using metal nano-particles and a method for manufacturing a chemical sensor using metal nano-particles are provided. The chemical sensor includes: metal nano-particles; single-ligand organic molecules (or a single molecule) that binds to the metal nano-particles by using a metal bonding functional group; a substrate bonding functional group formed at the metal nano-particles and the single-ligand organic molecules as bound to each other; a substrate; electrodes formed on the substrate and having an interdigitate (IDT) structure; and a substrate functional group formed on the substrate and positioned between the electrodes, wherein the substrate bonding functional group and the substrate functional group are covalently bonded.
    Type: Grant
    Filed: February 13, 2013
    Date of Patent: May 19, 2015
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Myung Lae Lee, Young Jun Kim, Sung Hae Jung, Ho Jun Ryu, Jong Moo Lee
  • Organometallic complexes and organic electroluminescence device using the same
    Patent number: 8945723
    Abstract: An organometallic complex that increases an energy band gap between HOMO and triplet MLCT states, and enables highly efficient phospholuminescence and can be used for an organic electroluminescent device. The organometallic complex, which is suitably used for forming an organic layer of the organic electroluminescent device, provides a luminescence maximum emission in the wavelength range of 400-650 nm, and induces white electroluminescence when combined with green or red luminescent materials.
    Type: Grant
    Filed: April 11, 2008
    Date of Patent: February 3, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventors: Eun-Sil Han, Das Rupasree Ragini, Seok Chang, Yi-Yeol Lyu, Jong-Hyoup Lee, Hae-Jung Son, Lyong-Sun Pu, Tae-Yong Noh
  • METHOD FOR PRODUCING Cu2ZnSnS4-xSex (0 LESS THAN-EQUAL TO X LESS THAN-EQUAL TO 4) THIN FILM BY ONE STEP ELECTRODEPOSITION IN ELECTROLYTIC BATH CONTAINING IONIC LIQUID
    Publication number: 20150027896
    Abstract: A Cu2ZnSnS4-xSex (0?x?4) thin film solar cell is disclosed. The thin film solar cell includes a Cu2ZnSnS4-xSex (0?x?4) thin film as an absorber layer produced by forming a precursor film composed of Cu, Zn, Sn, and Se using an ionic liquid as a solvent through a constant current process and annealing the precursor film with sulfur. Also disclosed is a method for fabricating the thin film solar cell. The method uses a non-vacuum electrodeposition process that is appropriate for large-area mass production and is thus cost effective compared to a vacuum process. In addition, since the method uses an ionic liquid, the formation of by-products harmful to humans as a result of side reactions is suppressed. Furthermore, the method uses a one-step electrodeposition process, which enables the deposition of a maximum of four elements at one time, or a multi-step deposition process, and an annealing process.
    Type: Application
    Filed: August 26, 2013
    Publication date: January 29, 2015
    Applicant: KOREA INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Jin Young Kim, Doh-Kwon Lee, Hong Gon Kim, Bong Soo Kim, Se Won Seo, Kee Doo Lee, Hae Jung Son, Min Jae Ko
  • METHOD AND APPARATUS FOR LOAD BALANCING IN COMMUNICATION SYSTEM
    Publication number: 20140372571
    Abstract: Provided is a method for balancing load of a server in a communication system. The method includes receiving, by a client, a new access request message; checking load status of servers that the client itself manages; selecting a lowest-load server among the servers as a server to which the client is to send the new access request message; and sending the new access request message to the selected server.
    Type: Application
    Filed: November 26, 2012
    Publication date: December 18, 2014
    Inventors: Hae-Jung Lim, Hong-Seok Yang, Jai-Jin Lim
  • Method of fabricating semiconductor device including a substrate attached to a carrier
    Patent number: 8912048
    Abstract: A method of fabricating a semiconductor device includes attaching a semiconductor substrate to a carrier using a carrier fixing layer, where the semiconductor substrate including a plurality of semiconductor chips. The method further includes forming gaps between adjacent ones of the chips. The gaps may be formed using one or more chemicals or light which act to remove portions of the semiconductor substrate to expose the carrier fixing layer. Additional portions of the carrier fixing layer are then removed to allow for removal of the chips from the carrier.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: December 16, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-Youn Kim, Ji-Hwang Kim, Hae-Jung Yu, Cha-Jea Jo
  • SEMICONDUCTOR DEVICE WITH BURIED BIT LINE AND METHOD FOR FABRICATING THE SAME
    Publication number: 20140306278
    Abstract: A semiconductor device includes an active body having two sidewalls facing each other in a lateral direction, a junction formed in a sidewall of the two sidewalls, a dielectric layer having an open portion to expose the junction and covering the active body, a junction extension portion having a buried region to fill the open portion, and a bit line coupled to the junction extension portion.
    Type: Application
    Filed: June 27, 2014
    Publication date: October 16, 2014
    Inventors: Sang-Do LEE, Hae-Jung LEE, Kyung-Bo KO
  • SEMICONDUCTOR PACKAGES INCLUDING A HEAT SPREADER AND METHODS OF FORMING THE SAME
    Publication number: 20140299980
    Abstract: Semiconductor packages including a heat spreader and methods of forming the same are provided. The semiconductor packages may include a first semiconductor chip, a second semiconductor chip, and a heat spreader stacked sequentially. The semiconductor packages may also include a thermal interface material (TIM) layer surrounding the second semiconductor chip and directly contacting a sidewall of the second semiconductor chip. An upper surface of the TIM layer may directly contact a lower surface of the heat spreader, and a sidewall of the TIM layer may be substantially coplanar with a sidewall of the heat spreader. In some embodiments, a sidewall of the first semiconductor chip may be substantially coplanar with the sidewall of the TIM layer.
    Type: Application
    Filed: January 21, 2014
    Publication date: October 9, 2014
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Eun-Kyoung Choi, Jong-Youn Kim, Sang-Wook Park, Hae-Jung Yu, In-Young Lee, Sang-Uk Han, Ji-Seok Hong
  • PACKAGE-ON-PACKAGE ELECTRONIC DEVICES INCLUDING SEALING LAYERS AND RELATED METHODS OF FORMING THE SAME
    Publication number: 20140273348
    Abstract: A package-on-package (POP) electronic device may include first and second packaging substrates, a solder interconnection providing electrical and mechanical coupling between the first and second packaging substrates, and first and second sealing layers between the first and second packaging substrates. The first and second sealing layers may be respective first and second epoxy sealing layers. Moreover, the second epoxy sealing layer may include a solder flux agent, and the first epoxy sealing layer may have a lower concentration of the solder flux agent than the second epoxy sealing layer.
    Type: Application
    Filed: May 28, 2014
    Publication date: September 18, 2014
    Inventors: Choongbin YIM, Hae-Jung YU, Taesung PARK
  • SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
    Publication number: 20140239478
    Abstract: A semiconductor device includes a first semiconductor chip at least partially overlapping a second semiconductor chip. The first semiconductor chip is coupled to a substrate and has a first width, and the second semiconductor chip has a second width. The device also includes a heat sink coupled to the second semiconductor chip and having a third width different from at least one of the first width or the second width. A package molding section at least partially overlaps a first area of the heat sink and does not overlap a second area of the heat sink which includes a top surface of the heat sink.
    Type: Application
    Filed: March 14, 2013
    Publication date: August 28, 2014
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ji-Seok HONG, Sang-Uk HAN, Eun-Kyoung CHOI, Jong-Youn KIM, Hae-Jung YU, Cha-Jea JO
  • METHOD OF FABRICATING SEMICONDUCTOR DEVICE
    Publication number: 20140213017
    Abstract: A method of fabricating a semiconductor device includes attaching a semiconductor substrate to a carrier using a carrier fixing layer, where the semiconductor substrate including a plurality of semiconductor chips. The method further includes forming gaps between adjacent ones of the chips. The gaps may be formed using one or more chemicals or light which act to remove portions of the semiconductor substrate to expose the carrier fixing layer. Additional portions of the carrier fixing layer are then removed to allow for removal of the chips from the carrier.
    Type: Application
    Filed: March 14, 2013
    Publication date: July 31, 2014
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jong-Youn KIM, Ji-Hwang KIM, Hae-Jung YU, Cha-Jea JO
  • Package-on-package electronic devices including sealing layers and related methods of forming the same
    Patent number: 8779606
    Abstract: A package-on-package (POP) electronic device may include first and second packaging substrates, a solder interconnection providing electrical and mechanical coupling between the first and second packaging substrates, and first and second sealing layers between the first and second packaging substrates. The first and second sealing layers may be respective first and second epoxy sealing layers. Moreover, the second epoxy sealing layer may include a solder flux agent, and the first epoxy sealing layer may have a lower concentration of the solder flux agent than the second epoxy sealing layer.
    Type: Grant
    Filed: January 4, 2013
    Date of Patent: July 15, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Choongbin Yim, Hae-Jung Yu, Taesung Park
  • Semiconductor device with buried bit line and method for fabricating the same
    Patent number: 8779422
    Abstract: A semiconductor device includes an active body having two sidewalls facing each other in a lateral direction, a junction formed in a sidewall of the two sidewalls, a dielectric layer having an open portion to expose the junction and covering the active body, a junction extension portion having a buried region to fill the open portion, and a bit line coupled to the junction extension portion.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: July 15, 2014
    Assignee: SK Hynix Inc.
    Inventors: Sang-Do Lee, Kyung-Bo Ko, Hae-Jung Lee
  • SEMICONDUCTOR DEVICES HAVING BURIED METAL SILICIDE LAYERS AND METHODS OF FABRICATING THE SAME
    Publication number: 20140175555
    Abstract: A semiconductor device includes a substrate and a plurality of active pillars disposed on the substrate and spaced apart from each other by trenches. Each of the active pillars includes a buried metal silicide pattern and an active region stacked on the buried metal silicide pattern, and the active region includes impurity junction regions.
    Type: Application
    Filed: March 15, 2013
    Publication date: June 26, 2014
    Applicant: SK HYNIX INC.
    Inventors: Sang Do LEE, Hae Jung LEE, Myoung Soo KIM, Sang Kil KANG
  • SEMICONDUCTING POLYMERS
    Publication number: 20140145119
    Abstract: Novel semiconducting photovoltaic polymers with conjugated units that provide improved solar conversion efficiency that can be used in electro-optical and electric devices. The polymers exhibit increased solar conversion efficiency in solar devices.
    Type: Application
    Filed: April 13, 2012
    Publication date: May 29, 2014
    Applicant: University of Chicago
    Inventors: Luping Yu, Hae Jung Son
  • SEMICONDUCTOR PACKAGE APPARATUS
    Publication number: 20140091463
    Abstract: According to example embodiments of inventive concepts, a semiconductor package apparatus includes a first semiconductor package including a first substrate, a first solder resist layer on the first substrate, and a first sealing member that covers and protects the first solder resist layer, and a plurality of solder balls on the first substrate. The plurality of solder balls includes a first solder ball having a first height and a second solder ball having a second height that is different from the first height. The first sealing member includes holes that expose the solder balls.
    Type: Application
    Filed: July 16, 2013
    Publication date: April 3, 2014
    Inventors: Hae-jung YU, Hak-kyoon BYUN, Kyung-tae NA, Seung-hun HAN, Tae-sung PARK, Choong-bin YIM
  • Apparatus for preventing stiction of MEMS microstructure
    Patent number: 8613287
    Abstract: An apparatus for preventing stiction of a three-dimensional MEMS (microelectromechanical system) microstructure, the apparatus including: a substrate; and a plurality of micro projections formed on a top surface of the substrate with a predetermined height in such a way that a cleaning solution flowing out from the microstructure disposed thereabove is discharged.
    Type: Grant
    Filed: April 14, 2008
    Date of Patent: December 24, 2013
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Chang Han Je, Myung Lae Lee, Sung Hae Jung, Gunn Hwang, Chang Auck Choi
  • Semiconductor device and method of fabricating the same
    Patent number: 8604561
    Abstract: In a semiconductor device and related method of fabricating the same, a hard mask layer is formed over a substrate, portions of the hard mask layer and the substrate are etched to form trenches having protruding portions at sidewalls, and an insulation layer buried in the trenches is formed to form device isolation regions having protruding portions at sidewalls, wherein the device isolation regions decrease a portion of a width of active regions.
    Type: Grant
    Filed: July 15, 2011
    Date of Patent: December 10, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventors: Yong-Tae Cho, Hae-Jung Lee, Eun-Mi Kim, Kyeong-Hyo Lee
  • Molded underfill flip chip package preventing warpage and void
    Patent number: 8592997
    Abstract: A molded underfill flip chip package may include a printed circuit board, a semiconductor chip mounted on the printed circuit board, and a sealant. The printed circuit board has at least one resin passage hole passing through the printed circuit board and at least one resin channel on a bottom surface of the printed circuit board, the at least one resin channel extending from the at least one resin passage hole passing through the printed circuit board. The sealant seals a top surface of the printed circuit board, the semiconductor chip, the at least one resin passage hole, and the at least one resin channel.
    Type: Grant
    Filed: November 1, 2010
    Date of Patent: November 26, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hae-jung Yu, Hyeong-seob Kim, Jong-ho Lee, Jin-woo Park
  • Educational robot
    Patent number: D695345
    Type: Grant
    Filed: December 16, 2011
    Date of Patent: December 10, 2013
    Assignee: KT Corporation
    Inventors: Hae-Jung Park, Heon-Moon Lim, Gun-Yong Lee, Min-Yong Kwon, Kyung Lee, Sung-Ju Hong