Abstract: A semiconductor device may include a calibration circuit and an output circuit. The calibration circuit may perform a calibration operation for setting a resistance value of the output circuit. The calibrations circuit may perform the calibration operation by being coupled, through a signal transmission line, to a reference resistor provided in another semiconductor device.

Abstract: A transmitting circuit may include a clock generation circuit and a serializer. The clock generation circuit may generate a plurality of output clock signals by performing an emphasis operation for a plurality of clock signals based on a plurality of data. The serializer may output the plurality of data as output data in synchronization with the plurality of output clock signals.

Abstract: A receiver circuit receives a signal from a semiconductor device. The receiver circuit includes an input buffer including a first plurality of transistors, the input buffer being configured to detect a fabrication condition of the receiver circuit, generate a control signal according to the detected fabrication condition, and control a gain of an input signal by adjusting a number of operating transistors among the first plurality of transistors in response to the control signal; and a latch circuit configured to latch an output signal of the input buffer, and adjust threshold voltages of a second plurality of transistors in response to a test signal.

Abstract: A semiconductor package for performing a reset operation includes a first semiconductor device including a first resistor element coupled to a reset pin, the first semiconductor device configured to be applied with a reset signal through the reset pin such that the reset operation is performed. The semiconductor package includes a second semiconductor device including a second resistor element coupled to the reset pin, the second semiconductor device configured to be applied with the reset signal through the reset pin such that the reset operation is performed. The first resistor element and the second resistor element may be selectively coupled to the reset pin when the reset operation is performed.

Abstract: A transmitting device includes a calibration circuit and a transmission circuit. The calibration circuit generates calibration codes by performing a calibration operation. The calibration circuit also generates compensation calibration codes by increasing or decreasing values of the calibration codes according to whether a number of codes among the calibration codes having a predetermined level is greater than or equal to a threshold value. The transmission circuit drives a signal transmission line based on an input signal and the compensation calibration codes.

Abstract: A semiconductor device may include a calibration circuit and an output circuit. The calibration circuit may perform a calibration operation for setting a resistance value of the output circuit. The calibrations circuit may perform the calibration operation by being coupled, through a signal transmission line, to a reference resistor provided in another semiconductor device.

Abstract: A receiver circuit may be provided. The receiver circuit may include a delay circuit and a synchronization circuit. The delay circuit may variably delay a data strobe signal based on a delay select signal. The synchronization circuit may generate internal data from data in synchronization with the variably delayed data strobe signal.

Abstract: A signal driver circuit includes a first inversion driver, a second inversion driver and an emphasis driver. The first inversion driver is configured to receive a first signal, and output a second signal by inversion-driving the first signal. The second inversion driver is configured to receive the second signal, and output a third signal by inversion-driving the second signal. The emphasis driver is configured to receive the third signal, inversion-drive the third signal, and combine the inversion-driven signal to the first signal.

Abstract: An amplification circuit is provided. The amplification circuit may include an amplification stage configured to amplify a first signal and a second signal, and generate third and fourth signals while in a first operation period. The amplification circuit may include a latch stage configured to latch the third and fourth signals while in a in a second operation period. The amplification circuit may supply a low voltage to the amplification stage during the first operation period, the low voltage to the latch stage during the second operation period, a high voltage to the amplification stage during the first operation period, and the high voltage to the latch stage during the second operation period.

Abstract: A transmitting device includes a calibration circuit and a transmission circuit. The calibration circuit generates calibration codes by performing a calibration operation. The calibration circuit also generates compensation calibration codes by increasing or decreasing values of the calibration codes according to whether a number of codes among the calibration codes having a predetermined level is greater than or equal to a threshold value. The transmission circuit drives a signal transmission line based on an input signal and the compensation calibration codes.

Abstract: A semiconductor device may include a calibration circuit and an output circuit. The calibration circuit may perform a calibration operation for setting a resistance value of the output circuit. The calibrations circuit may perform the calibration operation by being coupled, through a signal transmission line, to a reference resistor provided in another semiconductor device.

Abstract: A transmitting device includes a calibration circuit and a transmission circuit. The calibration circuit generates calibration codes by performing a calibration operation. The calibration circuit also generates compensation calibration codes by increasing or decreasing values of the calibration codes according to whether a number of codes among the calibration codes having a predetermined level is greater than or equal to a threshold value. The transmission circuit drives a signal transmission line based on an input signal and the compensation calibration codes.

Abstract: A semiconductor device may include a calibration circuit and an output circuit. The calibration circuit may perform a calibration operation for setting a resistance value of the output circuit. The calibrations circuit may perform the calibration operation by being coupled, through a signal transmission line, to a reference resistor provided in another semiconductor device.

Abstract: A data transmission circuit includes a data bus inversion encoding circuit configured to compare previous output data and current output data, invert or non-invert the current output data to control the number of data transitions; and transmitters configured to drive signal transmission lines based on outputs of the data bus inversion encoding circuit.

Abstract: A circuit may include a transmitter for generating a signal indicative of input data, an on-chip channel for transmitting the signal from the transmitter, and a receiver comprising a receiving terminal that has a negative resistance value as input resistance of the receiving terminal, the receiver generating a signal indicative of recovered data based on the transmitted signal through the on-chip channel. The circuit may recycle a portion of charge stored in the on-chip channel using charge recycling, and the charge recycling is associated with the negative resistance value of the input resistance.

Abstract: A serializer may be provided. The serializer may include a first data output circuit and a second data output circuit. The first data output circuit may provide first data to an output node in synchronization with a first phase clock and a second phase clock. The second data output circuit may provide second data to the output node in synchronization with the second phase clock and a third phase clock. The first data output circuit may perform a precharge operation or an emphasis operation for the second data output circuit, in synchronization with a third phase clock.

Abstract: A data transmission and reception system may include: a data transmission apparatus configured to generate N Tx signals having discrete levels using N binary data, and output the N Tx signals to N single-ended signal lines, respectively, where N is a natural number equal to or larger than 2; and a data reception apparatus configured to receive the N Tx signals transmitted in parallel through the single-ended signal lines, and restore the N binary data by comparing the received N Tx signals to each other.

Abstract: A transmission device may include a main driver configured to drive an output node based on an input signal, and may generate an output signal with multiple levels. The transmission device may include a variable emphasis driver configured to drive the output node with various driving forces based on transition information of the input signal.

Abstract: A system includes a data transmission unit, a termination resistor and a data reception unit. The data transmission unit may drive a data transmission line based on data, and drive the data transmission line to a voltage level corresponding to a termination voltage during a specified operation period. The termination resistor may be coupled between the data transmission line and a termination node. The data reception unit may receive a signal transmitted through the data transmission line.

Abstract: A serializer may be provided. The serializer may include a first data output circuit and a second data output circuit. The first data output circuit may provide first data to an output node in synchronization with a first phase clock and a second phase clock. The second data output circuit may provide second data to the output node in synchronization with the second phase clock and a third phase clock. The first data output circuit may perform a precharge operation or an emphasis operation for the second data output circuit, in synchronization with a third phase clock.