Abstract: A data output circuit of a semiconductor apparatus may include a first driver coupled to an output terminal via a first node, a second driver coupled to the output terminal via a second node and a controller coupled to the first and second drivers and configured to adjust a slew rate of a data signal output via the output terminal.

Abstract: An interface circuit may include a termination resistor and a termination voltage generation unit. The termination resistor may be coupled between a reception pad and a termination node. The termination voltage generation unit may detect a voltage level of the termination node, and may drive the termination node to a level of a termination voltage when the voltage level of the termination node deviates from a predetermined range.

Abstract: A system includes a data transmission unit, a termination resistor and a data reception unit. The data transmission unit may drive a data transmission line based on data, and drive the data transmission line to a voltage level corresponding to a termination voltage during a specified operation period. The termination resistor may be coupled between the data transmission line and a termination node. The data reception unit may receive a signal transmitted through the data transmission line.

Abstract: An interface circuit may include a termination resistor and a termination voltage generation unit. The termination resistor may be coupled between a reception pad and a termination node. The termination voltage generation unit may detect a voltage level of the termination node, and may drive the termination node to a level of a termination voltage when the voltage level of the termination node deviates from a predetermined range.

Abstract: A semiconductor device includes: a pre-emphasis control signal generation portion suitable for generating a pre-emphasis control signal for a pre-emphasis operation; and a plurality of output drivers, a portion of which performs the pre-emphasis operation based on the pre-emphasis control signal when an output operation is performed.

Abstract: A data output circuit of a semiconductor apparatus includes a pull-up driver electrically coupled between a power supply terminal and an output terminal, and configured to drive the output terminal in response to pull-up control signals. The data output circuit may also include a pull-down driver electrically coupled between the output terminal and a ground terminal, and configured to drive the output terminal in response to pull-down control signals. Further, the data output circuit may include a compensation unit configured to open a current path between the output terminal and the ground terminal during an operation period of the pull-up driver, and allow leakage current of the pull-up driver to flow through the current path.

Abstract: A data output circuit of a semiconductor apparatus is provided. The data output circuit may include a pull-up driver including a plurality of leg units configured to provide respective resistance values which are selected based on code signals, provide a total resistance value which is selected in response to one or more of the plurality of leg units being selectively activated based on selection signals, and configured to apply an output voltage with an output voltage level selected according to the selection of the total resistance value among a plurality of output voltage levels, to a data output pad. The data output circuit may include a control block configured to generate the selection signals in response to mode register signals. The data output circuit may include a code generator configured to generate the code signals based on a comparison of a reference voltage to a replica output voltage which varies according to an external resistance.

Abstract: A semiconductor device includes: a pre-emphasis control signal generation portion suitable for generating a pre-emphasis control signal for a pre-emphasis operation; and a plurality of output drivers, a portion of which performs the pre-emphasis operation based on the pre-emphasis control signal when an output operation is performed.

Abstract: A data output circuit of a semiconductor apparatus includes a pull-up driver including a plurality of leg units configured to be controlled in respective resistance values in response to code signals, be controlled in an entire resistance value as one or more of the plurality of leg units are selectively activated in response to selection signals, and configured to apply an output voltage with an output voltage level selected according to a control of the entire resistance value among a plurality of output voltage levels, to a data output pad; a control block configured to generate the selection signals in response to mode register signals; and a code generator configured to generate the code signals according to an external resistor.

Abstract: A data output circuit of a semiconductor apparatus includes a pull-up driver electrically coupled between a power supply terminal and an output terminal, and configured to drive the output terminal in response to pull-up control signals. The data output circuit may also include a pull-down driver electrically coupled between the output terminal and a ground terminal, and configured to drive the output terminal in response to pull-down control signals. Further, the data output circuit may include a compensation unit configured to open a current path between the output terminal and the ground terminal during an operation period of the pull-up driver, and allow leakage current of the pull-up driver to flow through the current path.

Abstract: A data output circuit of a semiconductor apparatus includes a pull-up driver electrically coupled between a power supply terminal and an output terminal, and configured to drive the output terminal in response to pull-up control signals. The data output circuit may also include a pull-down driver electrically coupled between the output terminal and a ground terminal, and configured to drive the output terminal in response to pull-down control signals. Further, the data output circuit may include a compensation unit configured to open a current path between the output terminal and the ground terminal during an operation period of the pull-up driver, and allow leakage current of the pull-up driver to flow through the current path.

Abstract: A data output circuit of a semiconductor apparatus includes a pull-up driver including a plurality of leg units configured to be controlled in respective resistance values in response to code signals, be controlled in an entire resistance value as one or more of the plurality of leg units are selectively activated in response to selection signals, and configured to apply an output voltage with an output voltage level selected according to a control of the entire resistance value among a plurality of output voltage levels, to a data output pad; a control block configured to generate the selection signals in response to mode register signals; and a code generator configured to generate the code signals according to an external resistor.

Abstract: A data output circuit of a semiconductor apparatus may include a first driver coupled to an output terminal via a first node, a second driver coupled to the output terminal via a second node and a controller coupled to the first and second drivers and configured to adjust a slew rate of a data signal output via the output terminal.

Abstract: A signal amplification circuit includes a differential amplification unit to differentially amplify an input signal and an input signal bar, to output to a first node and a second node, respectively, a first inverting element to output a first logic value to a first output node when the level of the amplified signal is higher than a logic threshold, and to output a second logic value to the first output node when the level of the amplified signal is lower than the logic threshold, a second inverting element to output the first logic value to a second output node when the level of the amplified signal bar is higher than the logic threshold, and to output the second logic value to the second output node when the level of the amplified signal bar is lower than the logic threshold, a first current path, and a second current path.

Abstract: A differential amplifier circuit includes a differential amplification unit configured to amplify a difference of an input signal and a reference voltage and generate an output signal and an output bar signal, a current source configured to control an amount of current flowing through the differential amplification unit, and a current control unit configured to control an amount of current of the current source based on a level of the input signal.

Abstract: An internal voltage generating circuit may include a first pull up resistor activated by a first range signal and connected between a pull up voltage terminal and a pull up common node; a second pull up resistor activated by a second range signal and connected between the pull up voltage terminal and the pull up common node; a first pull down resistor activated by the first range signal and connected between a pull down voltage terminal and a pull down common node; a second pull down resistor activated by the second range signal and connected between the pull down voltage terminal and the pull down common node; a resistor string including a plurality of series resistors connected between the pull up common node and the pull down common node; and a voltage selection circuit select voltage in response to voltage selection information.

Abstract: A signal amplification circuit includes a differential amplification unit to differentially amplify an input signal and an input signal bar, to output to a first node and a second node, respectively, a first inverting element to output a first logic value to a first output node when the level of the amplified signal is higher than a logic threshold, and to output a second logic value to the first output node when the level of the amplified signal is lower than the logic threshold, a second inverting element to output the first logic value to a second output node when the level of the amplified signal bar is higher than the logic threshold, and to output the second logic value to the second output node when the level of the amplified signal bar is lower than the logic threshold, a first current path, and a second current path.

Abstract: A differential amplifier circuit includes a differential amplification unit configured to amplify a difference of an input signal and a reference voltage and generate an output signal and an output bar signal, a current source configured to control an amount of current flowing through the differential amplification unit, and a current control unit configured to control an amount of current of the current source based on a level of the input signal.

Abstract: A transmitter system for transmitting parallel data by compensating a crosstalk includes: first and second transmission lines parallel to each other; a first inverted crosstalk pulse generation unit configured to receive first transmission data and inverted first transmission data and output a first inverted crosstalk pulse according to a data mode; a second inverted crosstalk pulse generation unit configured to receive second transmission data transmitted in parallel to the first transmission data and inverted second transmission data and output a second inverted crosstalk pulse according to the data mode; a first addition unit configured to combine the first transmission data and the second inverted crosstalk pulse and output first compensation data to be transmitted to the first transmission line; and a second addition unit configured to combine the second transmission data and the first inverted crosstalk pulse and output second compensation data to be transmitted to the second transmission line.

Abstract: An internal voltage generating circuit may include a first pull up resistor activated by a first range signal and connected between a pull up voltage terminal and a pull up common node; a second pull up resistor activated by a second range signal and connected between the pull up voltage terminal and the pull up common node; a first pull down resistor activated by the first range signal and connected between a pull down voltage terminal and a pull down common node; a second pull down resistor activated by the second range signal and connected between the pull down voltage terminal and the pull down common node; a resistor string including a plurality of series resistors connected between the pull up common node and the pull down common node; and a voltage selection circuit select voltage in response to voltage selection information.