Abstract: A system includes a data transmission unit, a termination resistor and a data reception unit. The data transmission unit may drive a data transmission line based on data, and drive the data transmission line to a voltage level corresponding to a termination voltage during a specified operation period. The termination resistor may be coupled between the data transmission line and a termination node. The data reception unit may receive a signal transmitted through the data transmission line.

Abstract: A semiconductor apparatus may include a receiver circuit and a termination circuit. The receiver circuit may be coupled to a receiving node, and configured to receive a signal transmitted through a signal transmission line. The termination circuit may be configured to be turned on to set a resistance value of the receiving node in a transition period of the signal, and turned off in a stabilization period of the signal.

Abstract: A data transmission and reception system may include: a data transmission apparatus configured to generate N Tx signals having discrete levels using N binary data, and output the N Tx signals to N single-ended signal lines, respectively, where N is a natural number equal to or larger than 2; and a data reception apparatus configured to receive the N Tx signals transmitted in parallel through the single-ended signal lines, and restore the N binary data by comparing the received N Tx signals to each other.

Abstract: A data transmission device may include a calibration circuit and an output driver. The calibration circuit may generate a pull-up calibration voltage and a pull-down calibration voltage. The resistance value of the output driver may be changed based on the pull-up calibration voltage and the pull-down calibration voltage.

Abstract: An impedance calibration device for a semiconductor device includes a process sensor that detects a process condition for the semiconductor device and outputs a process signal, a temperature monitoring sensor that detects a temperature of the semiconductor device and outputs a temperature signal, a converter that converts the process signal and the temperature signal into a digital signal, and a code generation circuit that generates and outputs a driving code for controlling a level of a voltage at an output node according to the digital signal of the converter and a data signal. The impedance calibration device further includes an output driver that pulls up or pulls down the voltage at the output node according to the driving code.

Abstract: A serializer may be provided. The serializer may include a first data output circuit and a second data output circuit. The first data output circuit may provide first data to an output node in synchronization with a first phase clock and a second phase clock. The second data output circuit may provide second data to the output node in synchronization with the second phase clock and a third phase clock. The first data output circuit may perform a precharge operation or an emphasis operation for the second data output circuit, in synchronization with a third phase clock.

Abstract: A receiver circuit may be provided. The receiver circuit may include a delay circuit and a synchronization circuit. The delay circuit may variably delay a data strobe signal based on a delay select signal. The synchronization circuit may generate internal data from data in synchronization with the variably delayed data strobe signal.

Abstract: A data transmission and reception system may include: a data transmission apparatus configured to generate N Tx signals having discrete levels using N binary data, and output the N Tx signals to N single-ended signal lines, respectively, where N is a natural number equal to or larger than 2; and a data reception apparatus configured to receive the N Tx signals transmitted in parallel through the single-ended signal lines, and restore the N binary data by comparing the received N Tx signals to each other.

Abstract: A semiconductor device may include a calibration circuit and an output circuit. The calibration circuit may perform a calibration operation for setting a resistance value of the output circuit. The calibrations circuit may perform the calibration operation by being coupled, through a signal transmission line, to a reference resistor provided in another semiconductor device.

Abstract: A data transmission device may include a calibration circuit and an output driver. The calibration circuit may generate a pull-up calibration voltage and a pull-down calibration voltage. The resistance value of the output driver may be changed based on the pull-up calibration voltage and the pull-down calibration voltage.

Abstract: A buffer includes an amplification circuit, an amplification current generation circuit, and a latch. The amplification circuit may change voltage levels of a first output node and a second output node based on a clock signal and a pair of input signals. The amplification current generation circuit may provide currents having different magnitudes to the first and second output nodes during a first operation period, and may provide currents having the same magnitude to the first and second output nodes during a second operation period. The latch circuit may latch the voltage levels of the first output node and the second output node based on the clock signal.

Abstract: An impedance calibration device for a semiconductor device includes a process sensor that detects a process condition for the semiconductor device and outputs a process signal, a temperature monitoring sensor that detects a temperature of the semiconductor device and outputs a temperature signal, a converter that converts the process signal and the temperature signal into a digital signal, and a code generation circuit that generates and outputs a driving code for controlling a level of a voltage at an output node according to the digital signal of the converter and a data signal. The impedance calibration device further includes an output driver that pulls up or pulls down the voltage at the output node according to the driving code.

Abstract: A buffer includes an amplification circuit, an amplification current generation circuit, and a latch. The amplification circuit may change voltage levels of a first output node and a second output node based on a clock signal and a pair of input signals. The amplification current generation circuit may provide currents having different magnitudes to the first and second output nodes during a first operation period, and may provide currents having the same magnitude to the first and second output nodes during a second operation period. The latch circuit may latch the voltage levels of the first output node and the second output node based on the clock signal.

Abstract: A serializer may be provided. The serializer may include a first data output circuit and a second data output circuit. The first data output circuit may provide first data to an output node in synchronization with a first phase clock and a second phase clock. The second data output circuit may provide second data to the output node in synchronization with the second phase clock and a third phase clock. The first data output circuit may perform a precharge operation or an emphasis operation for the second data output circuit, in synchronization with a third phase clock.

Abstract: A semiconductor device includes: a pre-emphasis control signal generation block suitable for generating first and second pre-emphasis control signals for controlling a pre-emphasis operation; at least one first output driver suitable for being selectively enabled in response to a selection code signal and driving a pad in response to a first output signal; and at least one second output driver suitable for being selectively enabled in response to the selection code signal and the first pre-emphasis control signal, performing the pre-emphasis operation with a driving force corresponding to a calibration code signal, and performing the pre-emphasis operation with a maximum driving force in response to the second pre-emphasis control signal.

Abstract: A transmission device may include a main driver configured to drive an output node based on an input signal, and may generate an output signal with multiple levels. The transmission device may include a variable emphasis driver configured to drive the output node with various driving forces based on transition information of the input signal.

Abstract: A data transmission and reception system may include: a data transmission apparatus configured to generate N Tx signals having discrete levels using N binary data, and output the N Tx signals to N single-ended signal lines, respectively, where N is a natural number equal to or larger than 2; and a data reception apparatus configured to receive the N Tx signals transmitted in parallel through the single-ended signal lines, and restore the N binary data by comparing the received N Tx signals to each other.

Abstract: A data output circuit of a semiconductor apparatus includes a pull-up driver including a first plurality of leg units commonly electrically coupled to a data output pad and configured to pull up the data output pad in response to a first code signals, a pull-down driver including a second plurality of leg units commonly electrically coupled to the data output pad and configured to pull down the data output pad to a second code signals, and a code generator configured to generate the first and second code signals. The code generator generates the second code signals by comparing a replica voltage to a reference voltage.

Abstract: A transmission device may include a main driver configured to drive an output node based on an input signal, and may generate an output signal with multiple levels. The transmission device may include a variable emphasis driver configured to drive the output node with various driving forces based on transition information of the input signal.

Abstract: A semiconductor device includes: a pre-emphasis control signal generation block suitable for generating first and second pre-emphasis control signals for controlling a pre-emphasis operation; at least one first output driver suitable for being selectively enabled in response to a selection code signal and driving a pad in response to a first output signal; and at least one second output driver suitable for being selectively enabled in response to the selection code signal and the first pre-emphasis control signal, performing the pre-emphasis operation with a driving force corresponding to a calibration code signal, and performing the pre-emphasis operation with a maximum driving force in response to the second pre-emphasis control signal.