Abstract: The present disclosure provides a method that includes providing a substrate having a first dielectric material layer and first conductive features that are laterally separated from each other by segments of the first dielectric material layer; depositing a first etch stop layer on the first dielectric material layer and the first conductive features, thereby forming the first etch stop layer having oxygen-rich portions self-aligned with the segments of the first dielectric material layer and oxygen-poor portions self-aligned with the first conductive features; performing a selective removal process to selectively remove the oxygen-poor portions of the first etch stop layer; forming a second etch stop layer on the first conductive features and the oxygen-rich portions of the first etch stop layer; forming a second dielectric material layer on the second etch stop layer; and forming a conductive structure in the second dielectric material layer.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a first conductive structure over the substrate. The semiconductor device structure includes a first dielectric layer over the substrate. The first dielectric layer has a first opening exposing the first conductive structure. The semiconductor device structure includes a cover layer covering a first inner wall of the first opening. The cover layer has a second opening exposing the first conductive structure. The cover layer includes a metal oxide. The semiconductor device structure includes a second conductive structure filled in the first opening and surrounded by the cover layer. The second conductive structure is electrically connected to the first conductive structure.

Abstract: A method embodiment for patterning a semiconductor device includes patterning a dummy layer over a hard mask to form one or more dummy lines. A sidewall aligned spacer is conformably formed over the one or more dummy lines and the hard mask. A first reverse material layer is formed over the sidewall aligned spacer. A first photoresist is formed and patterned over the first reverse material layer. The first reverse material layer using the first photoresist as a mask, wherein the sidewall aligned spacer is not etched. The one or more dummy lines are removed, and the hard mask is patterned using the sidewall aligned spacer and the first reverse material layer as a mask. A material used for forming the sidewall aligned spacer has a higher selectivity than a material used for forming the first reverse material layer.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a dielectric layer over the semiconductor substrate. The dielectric layer has a protection region and a lower portion that is between the protection region and the semiconductor substrate. The protection region contains more carbon than the dielectric layer. The semiconductor device structure also includes a conductive feature penetrating through the protection region, and a lower portion of the conductive feature is surrounded by the lower portion of the dielectric layer.

Abstract: A first conductive element is disposed. in a first dielectric layer. An etching stop layer is disposed on the first dielectric layer but not on the first conductive element. A first metal capping layer segment is disposed on the first conductive element but not on the first dielectric layer. The etching stop layer has a greater thickness than the first metal capping layer segment. A first segment of a second conductive element is disposed on the first metal capping layer segment. A second segment of the second conductive element is disposed over the first segment of the second conductive element and partially over the etching stop layer. A third conductive element is disposed over the second conductive element.

Abstract: The present disclosure provides a method for forming an integrated circuit (IC) structure. The method comprises providing a substrate including a conductive feature; forming aluminum (Al)-containing dielectric layer on the conductive feature; forming a low-k dielectric layer on the Al-containing dielectric layer; and etching the low-k dielectric layer to form a contact trench aligned with the conductive feature. A bottom of the contact trench is on a surface of the Al-containing dielectric layer.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a first conductive structure over the substrate. The semiconductor device structure includes a first dielectric layer over the substrate. The first dielectric layer has a first opening exposing the first conductive structure. The semiconductor device structure includes a cover layer covering a first inner wall of the first opening. The cover layer has a second opening exposing the first conductive structure. The cover layer includes a metal oxide. The semiconductor device structure includes a second conductive structure filled in the first opening and surrounded by the cover layer. The second conductive structure is electrically connected to the first conductive structure.

Abstract: A method for fabricating a semiconductor structure includes providing a substrate and a first layer over the substrate, wherein the first layer includes one or more overlay marks. The method further includes forming one or more layers on the first layer and performing a dark field (DF) inspection on the one or more overlay marks underlying the one or more layers to receive a post-film-formation data.

Abstract: A semiconductor device includes a first metal wiring layer, an interlayer insulating layer formed over the first metal layer, a second metal wiring structure embedded in the interlayer dielectric layer and connected to the first metal wiring layer, and an etch-stop layer disposed between the first metal wiring and the first interlayer dielectric layer. The etch-stop layer includes one or more sub-layers. The etch-stop layer includes a first sub-layer made of an aluminum-based insulating material, hafnium oxide, zirconium oxide or titanium oxide.

Abstract: A layer of an interconnect structure is formed over a substrate. The layer contains an interlayer dielectric (ILD) material and a metal line disposed in the ILD. A first etching stop layer is formed on the ILD but not on the metal line. The first etching stop layer is formed through a selective atomic layer deposition (ALD) process. A second etching stop layer is formed over the first etching stop layer. A high etching selectivity exists between the first and second etching stop layers. A via is formed to be at least partially aligned with, and electrically coupled to, the metal line. The first etching stop layer prevents the ILD from being etched through during the formation of the via.

Abstract: Some embodiments relate to a method of processing a workpiece. The workpiece includes a first surface region having a first wettability coefficient, and a second surface region having a second wettability coefficient that differs from the first wettability coefficient. A liquid, which corresponds to an optical structure, is dispensed on the first and second surface regions of the workpiece, wherein the liquid self-aligns to the second surface region due to the difference between the first and second wettability coefficients. The self-aligned liquid is hardened to form the optical structure.

Abstract: Semiconductor device metallization systems and methods are disclosed. In some embodiments, a metallization system for semiconductor devices includes a mainframe, and a plurality of modules disposed proximate the mainframe. One of the plurality of modules comprises a physical vapor deposition (PVD) module and one of the plurality of modules comprises an ultraviolet light (UV) cure module.

Abstract: The present disclosure provides a method that includes providing a substrate having a first dielectric material layer and first conductive features that are laterally separated from each other by segments of the first dielectric material layer; depositing a first etch stop layer on the first dielectric material layer and the first conductive features, thereby forming the first etch stop layer having oxygen-rich portions self-aligned with the segments of the first dielectric material layer and oxygen-poor portions self-aligned with the first conductive features; performing a selective removal process to selectively remove the oxygen-poor portions of the first etch stop layer; forming a second etch stop layer on the first conductive features and the oxygen-rich portions of the first etch stop layer; forming a second dielectric material layer on the second etch stop layer; and forming a conductive structure in the second dielectric material layer.

Abstract: A layer of an interconnect structure is formed over a substrate. The layer contains an interlayer dielectric (ILD) material and a metal line disposed in the ILD. A first etching stop layer is formed on the ILD but not on the metal line. The first etching stop layer is formed through a selective atomic layer deposition (ALD) process. A second etching stop layer is formed over the first etching stop layer. A high etching selectivity exists between the first and second etching stop layers. A via is formed to be at least partially aligned with, and electrically coupled to, the metal line. The first etching stop layer prevents the ILD from being etched through during the formation of the via.

Abstract: A plurality of high-k metal gate (HKMG) structures is formed over a substrate. The (HKMG) structures are separated by a plurality of gaps. The HKMG structures each include a first dielectric layer at an upper surface of the HKMG structure. The gaps are filled with a first conductive material. A portion of the first conductive material is removed in each of the gaps through an etching-back process. A metal oxide layer is formed using a spin-on deposition process. The metal oxide layer is formed over the (HKMG) structures and over the first conductive material. A second dielectric layer is formed over the metal oxide layer. An opening is etched in the second dielectric layer. The opening is etched through the second dielectric layer and through the metal oxide layer. The opening is filled with a second conductive material.

Abstract: A method comprises forming a plateau region and a trench region over a substrate, wherein the trench region comprises a slope and a flat bottom, depositing a reflecting layer over the flat bottom and a portion of the slope, depositing a first adhesion promoter layer over the reflecting layer, applying a first curing process to the first adhesion promoter layer, wherein, after the first curing process finishes, the reflecting layer and the first adhesion promoter layer form a first bonding interface, depositing a bottom cladding layer deposited over the first adhesion promoter layer, applying a second curing process to the bottom cladding layer to form a second bonding interface layer, depositing a core layer over the bottom cladding layer and depositing a top cladding layer over the core layer.

Abstract: A system and method of etching a semiconductor device are provided. Etching solution is sampled and analyzed by a monitoring unit to determine a concentration of components within the etching solution, such as an oxidant concentration. Then, based upon such measurement, a makeup amount of the components may be added be a makeup unit to the etching solution to control the concentration of the components within the etching system.

Abstract: A method of forming a semiconductor device includes providing a precursor. The precursor includes a substrate; a gate stack over the substrate; a first dielectric layer over the gate stack; a gate spacer on sidewalls of the gate stack and on sidewalls of the first dielectric layer; and source and drain (S/D) contacts on opposing sides of the gate stack. The method further includes recessing the gate spacer to at least partially expose the sidewalls of the first dielectric layer but not to expose the sidewalls of the gate stack. The method further includes forming a spacer protection layer over the gate spacer, the first dielectric layer, and the S/D contacts.

Abstract: A system and method for manufacturing semiconductor devices is provided. An embodiment comprises using an etchant to remove a portion of a substrate to form an opening with a 45° angle with a major surface of the substrate. The etchant comprises a base, a surfactant, and an oxidant. The oxidant may be hydrogen peroxide.

Abstract: Embodiments of forming a waveguide structure are provided. The waveguide structure includes a substrate, and the substrate has an interconnection region and a waveguide region. The waveguide structure also includes a trench formed in the substrate, and the trench has a sloping sidewall surface and a substantially flat bottom. The waveguide structure further includes a bottom cladding layer formed on the substrate, and the bottom cladding layer extends from the interconnection region to the waveguide region, and the bottom cladding layer acts as an insulating layer in the interconnection region. The waveguide structure further includes a metal layer formed on the bottom cladding layer on the sloping sidewall surface.