Patents by Inventor Hai-Ching Chen
Hai-Ching Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8729703Abstract: A method of forming a semiconductor structure includes providing a substrate; forming a low-k dielectric layer over the substrate; embedding a conductive wiring into the low-k dielectric layer; and thermal soaking the conductive wiring in a carbon-containing silane-based chemical to form a barrier layer on the conductive wiring. A lining barrier layer is formed in the opening for embedding the conductive wiring. The lining barrier layer may comprise same materials as the barrier layer, and the lining barrier layer may be recessed before forming the barrier layer and may contain a metal that can be silicided.Type: GrantFiled: May 9, 2013Date of Patent: May 20, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Hai-Ching Chen, Tien-I Bao
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Publication number: 20140091477Abstract: A method for forming a field-effect transistor with a raised drain structure is disclosed. The method includes depositing a low-k inter-metal layer over a semiconductor substrate, depositing a porogen-containing low-k layer over the low-k inter-metal layer, and etching a space for the via through the low-k inter-metal layer and the porogen-containing low-k layer. The method further includes depositing a metal layer, a portion of the metal layer filling the space for the via, another portion of the metal layer being over the porogen-containing low-layer, removing the portion of the metal layer over the porogen-containing layer by a CMP process, and curing the porogen-containing low-k layer to form a cured low-k layer.Type: ApplicationFiled: September 28, 2012Publication date: April 3, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yung-Hsu Wu, Shih-Kang Fu, Hsin-Chieh Yao, Chia-Min Lin, Hsiang-Huan Lee, Chung-Ju Lee, Hai-Ching Chen, Shau-Lin Shue
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Publication number: 20140084421Abstract: A structure comprises a substrate having a plateau region and a trench region, a reflecting layer formed over a top surface of the trench region, a first adhesion promoter layer formed over the reflecting layer, a bottom cladding layer deposited over the first adhesion promoter layer, a core layer formed over the bottom cladding layer and a top cladding layer formed over the core layer.Type: ApplicationFiled: September 27, 2012Publication date: March 27, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chun-Hao Tseng, Ying-Hao Kuo, Kai-Feng Cheng, Hai-Ching Chen, Tien-I Bao
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Publication number: 20140021611Abstract: The present disclosure is directed to a method of manufacturing an interconnect structure in which a low-k dielectric layer is formed over a semiconductor substrate followed by formation of a copper or copper alloy layer over the low-k dielectric layer. The copper or copper alloy layer is patterned and etched to form a copper body having recesses, which are then filled with a low-k dielectric material. The method allows for formation of a damascene structures without encountering the various problems presented by non-planar features and by porus low-K dielectric damage.Type: ApplicationFiled: July 17, 2012Publication date: January 23, 2014Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ming Han Lee, Hai-Ching Chen, Hsiang-Huan Lee, Tien-I Bao, Chi-Lin Teng
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Patent number: 8629066Abstract: An integrated circuit structure includes a semiconductor substrate; a through-semiconductor via (TSV) opening extending into the semiconductor substrate; and a TSV liner in the TSV opening. The TSV liner includes a sidewall portion on a sidewall of the TSV opening and a bottom portion at a bottom of the TSV opening. The bottom portion of the TSV liner has a bottom height greater than a middle thickness of the sidewall portion of the TSV liner.Type: GrantFiled: July 30, 2012Date of Patent: January 14, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ching-Yu Lo, Hung-Jung Tu, Hai-Ching Chen, Tien-I Bao, Wen-Chih Chiou, Chen-Hua Yu
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Publication number: 20130228927Abstract: A semiconductor structure includes a first dielectric layer over a substrate. At least one first conductive structure is within the first dielectric layer. The first conductive structure includes a cap portion extending above a top surface of the first dielectric layer. At least one first dielectric spacer is on at least one sidewall of the cap portion of the first conductive structure.Type: ApplicationFiled: April 23, 2013Publication date: September 5, 2013Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chen-Hua YU, Hai-Ching CHEN, Tien-I BAO
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Publication number: 20130223789Abstract: An optical bench on substrate includes a substrate and a trench formed inside the substrate and having a sloping side. A reflector layer is formed over the sloping side. An optical component is mounted over the substrate. The reflector layer is configured to reflect an electromagnetic wave to or from the optical component.Type: ApplicationFiled: February 23, 2012Publication date: August 29, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wan-Yu LEE, Chun-Hao TSENG, Hai-Ching CHEN, Tien-I BAO
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Publication number: 20130216177Abstract: A method of fabricating a waveguide device is disclosed. The method includes providing a substrate having an elector-interconnection region and a waveguide region and forming a patterned dielectric layer and a patterned redistribution layer (RDL) over the substrate in the electro-interconnection region. The method also includes bonding the patterned RDL to a vertical-cavity surface-emitting laser (VCSEL) through a bonding stack. A reflecting-mirror trench is formed in the substrate in the waveguide region, and a reflecting layer is formed over a reflecting-mirror region inside the waveguide region. The method further includes forming and patterning a bottom cladding layer in a wave-tunnel region inside the waveguide region and forming and patterning a core layer and a top cladding layer in the waveguide region.Type: ApplicationFiled: February 17, 2012Publication date: August 22, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chun-Hao Tseng, Wan-Yu Lee, Hai-Ching Chen, Tien-I Bao
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Patent number: 8446012Abstract: A semiconductor structure includes a first dielectric layer over a substrate. At least one first conductive structure is within the first dielectric layer. The first conductive structure includes a cap portion extending above a top surface of the first dielectric layer. At least one first dielectric spacer is on at least one sidewall of the cap portion of the first conductive structure.Type: GrantFiled: May 11, 2007Date of Patent: May 21, 2013Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chen-Hua Yu, Hai-Ching Chen, Tien-I. Bao
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Patent number: 8440564Abstract: A method of forming a semiconductor structure includes providing a substrate; forming a low-k dielectric layer over the substrate; embedding a conductive wiring into the low-k dielectric layer; and thermal soaking the conductive wiring in a carbon-containing silane-based chemical to form a barrier layer on the conductive wiring. A lining barrier layer is formed in the opening for embedding the conductive wiring. The lining barrier layer may comprise same materials as the barrier layer, and the lining barrier layer may be recessed before forming the barrier layer and may contain a metal that can be silicided.Type: GrantFiled: July 17, 2012Date of Patent: May 14, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Hai-Ching Chen, Tien-I Bao
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Patent number: 8405192Abstract: The present disclosure provides a dielectric material including a low dielectric constant material and an additive. The additive includes a compound having a Si—X—Si bridge, where X is a number of carbon atoms between 1 and 8. The additive may include terminal Si—CH3 groups. The dielectric material including the additive may be used as an inter-layer dielectric (ILD) layer of a semiconductor device. The dielectric material including the additive may be formed using a CVD or sol-gel process. One example of the additive is bis(triethoxysilyl)ethene.Type: GrantFiled: September 29, 2010Date of Patent: March 26, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsin-Yen Huang, Ching-Yu Lo, Hai-Ching Chen, Tien-I Bao
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Publication number: 20130069234Abstract: The present disclosure provides one embodiment of a method to form an interconnect structure. The method includes forming a first dielectric material layer on a substrate; patterning the first dielectric material layer to form a plurality of vias therein; forming a metal layer on the first dielectric layer and the substrate, wherein the metal layer fills in the plurality of vias; and etching the metal layer such that portions of the metal layer above the first dielectric material layer are patterned to form a plurality of metal lines, aligned with plurality of vias, respectively.Type: ApplicationFiled: September 19, 2011Publication date: March 21, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chung-Ju Lee, Tien-I Bao, Ming-Shih Yeh, Hai-Ching Chen, Shau-Lin Shue
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Publication number: 20120289062Abstract: An integrated circuit structure includes a semiconductor substrate; a through-semiconductor via (TSV) opening extending into the semiconductor substrate; and a TSV liner in the TSV opening. The TSV liner includes a sidewall portion on a sidewall of the TSV opening and a bottom portion at a bottom of the TSV opening. The bottom portion of the TSV liner has a bottom height greater than a middle thickness of the sidewall portion of the TSV liner.Type: ApplicationFiled: July 30, 2012Publication date: November 15, 2012Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ching-Yu Lo, Hung-Jung Tu, Hai-Ching Chen, Tien-I Bao, Wen-Chih Chiou, Chen-Hua Yu
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Publication number: 20120282768Abstract: A method of forming a semiconductor structure includes providing a substrate; forming a low-k dielectric layer over the substrate; embedding a conductive wiring into the low-k dielectric layer; and thermal soaking the conductive wiring in a carbon-containing silane-based chemical to form a barrier layer on the conductive wiring. A lining barrier layer is formed in the opening for embedding the conductive wiring. The lining barrier layer may comprise same materials as the barrier layer, and the lining barrier layer may be recessed before forming the barrier layer and may contain a metal that can be silicided.Type: ApplicationFiled: July 17, 2012Publication date: November 8, 2012Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Hai-Ching Chen, Tien-I Bao
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Patent number: 8264066Abstract: An integrated circuit structure includes a semiconductor substrate; a through-semiconductor via (TSV) opening extending into the semiconductor substrate; and a TSV liner in the TSV opening. The TSV liner includes a sidewall portion on a sidewall of the TSV opening and a bottom portion at a bottom of the TSV opening. The bottom portion of the TSV liner has a bottom height greater than a middle thickness of the sidewall portion of the TSV liner.Type: GrantFiled: November 13, 2009Date of Patent: September 11, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ching-Yu Lo, Hung-Jung Tu, Hai-Ching Chen, Tien-I Bao, Wen-Chih Chiou, Chen-Hua Yu
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Patent number: 8232201Abstract: A method of forming a semiconductor structure includes providing a substrate; forming a low-k dielectric layer over the substrate; embedding a conductive wiring into the low-k dielectric layer; and thermal soaking the conductive wiring in a carbon-containing silane-based chemical to form a barrier layer on the conductive wiring. A lining barrier layer is formed in the opening for embedding the conductive wiring. The lining barrier layer may comprise same materials as the barrier layer, and the lining barrier layer may be recessed before forming the barrier layer and may contain a metal that can be silicided.Type: GrantFiled: May 25, 2011Date of Patent: July 31, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Hai-Ching Chen, Tien-I Bao
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Publication number: 20120074535Abstract: The present disclosure provides a dielectric material including a low dielectric constant material and an additive. The additive includes a compound having a Si—X—Si bridge, where X is a number of carbon atoms between 1 and 8. The additive may include terminal Si—CH3 groups. The dielectric material including the additive may be used as an inter-layer dielectric (ILD) layer of a semiconductor device. The dielectric material including the additive may be formed using a CVD or sol-gel process. One example of the additive is bis(triethoxysilyl)ethene.Type: ApplicationFiled: September 29, 2010Publication date: March 29, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., ("TSMC")Inventors: Hsin-Yen Huang, Ching-Yu Lo, Hai-Ching Chen, Tien-I Bao
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Publication number: 20110223762Abstract: A method of forming a semiconductor structure includes providing a substrate; forming a low-k dielectric layer over the substrate; embedding a conductive wiring into the low-k dielectric layer; and thermal soaking the conductive wiring in a carbon-containing silane-based chemical to form a barrier layer on the conductive wiring. A lining barrier layer is formed in the opening for embedding the conductive wiring. The lining barrier layer may comprise same materials as the barrier layer, and the lining barrier layer may be recessed before forming the barrier layer and may contain a metal that can be silicided.Type: ApplicationFiled: May 25, 2011Publication date: September 15, 2011Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Hai-Ching Chen, Tien-I Bao
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Patent number: 7964496Abstract: A method of forming a semiconductor structure includes providing a substrate; forming a low-k dielectric layer over the substrate; embedding a conductive wiring into the low-k dielectric layer; and thermal soaking the conductive wiring in a carbon-containing silane-based chemical to form a barrier layer on the conductive wiring. A lining barrier layer is formed in the opening for embedding the conductive wiring. The lining barrier layer may comprise same materials as the barrier layer, and the lining barrier layer may be recessed before forming the barrier layer and may contain a metal that can be silicided.Type: GrantFiled: November 21, 2006Date of Patent: June 21, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Hai-Ching Chen, Tien-I Bao
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Publication number: 20110115088Abstract: An integrated circuit device has a dual damascene structure including a lower via portion and an upper line portion. The lower via portion is formed in a polyimide layer, and the upper line portion is formed in an inter-metal dielectric (IMD) layer formed of USG or polyimide. A passivation layer is formed on the IMD layer, and a bond pad is formed overlying the passivation layer to electrically connect the upper line portion.Type: ApplicationFiled: November 19, 2009Publication date: May 19, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ching-Yu Lo, Bo-Jiun Lin, Hai-Ching Chen, Tien-I Bao, Shau-Lin Shue, Chen-Hua Yu