Patents by Inventor Hai-Dang Trinh

Hai-Dang Trinh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250151635
    Abstract: Various embodiments of the present disclosure are directed towards an integrated chip comprising a first electrode overlying a substrate. A first data storage layer overlies the first electrode. The first data storage layer comprises a metal oxide. The metal oxide comprises a first metal, a second metal, and a nonmetal. The first metal is different from the second metal. An atomic percentage of the nonmetal is less than an atomic percentage of the second metal. A second electrode overlies the first data storage layer.
    Type: Application
    Filed: January 10, 2025
    Publication date: May 8, 2025
    Inventors: Bi-Shen Lee, Hai-Dang Trinh, Fa-Shen Jiang, Hsun-Chung Kuang
  • Patent number: 12295270
    Abstract: The present disclosure relates to a resistive random access memory (RRAM) device. In some embodiments, the RRAM device includes a first electrode disposed over a substrate and a second electrode over the first electrode. A doped data storage structure is disposed between the first electrode and the second electrode. The doped data storage structure has a dopant with a doping concentration profile that is asymmetric over a height of the doped data storage structure and that has a maximum dopant concentration at non-zero distances from a top surface and a bottom surface of the doped data storage structure.
    Type: Grant
    Filed: October 27, 2021
    Date of Patent: May 6, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Fa-Shen Jiang, Cheng-Yuan Tsai, Hai-Dang Trinh, Hsing-Lien Lin, Bi-Shen Lee
  • Patent number: 12295267
    Abstract: A semiconductor device and method of manufacturing the same are provided. The semiconductor device includes a substrate, a first dielectric layer, an etching stop layer, a second dielectric layer, a conductive via, and a data storage structure. The first dielectric layer is disposed on the substrate. The etching stop layer is disposed on the first dielectric layer. The second dielectric layer is disposed on the etching stop layer. The first dielectric layer, the etching stop layer, and the second dielectric layer collectively define an opening. The conductive via is disposed in the opening. The data storage structure is disposed on the conductive via.
    Type: Grant
    Filed: April 29, 2022
    Date of Patent: May 6, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Bi-Shen Lee, Hai-Dang Trinh, Hsun-Chung Kuang
  • Patent number: 12261197
    Abstract: Various embodiments of the present disclosure are directed towards a method for forming an integrated chip. The method includes forming a bottom electrode over a substrate. A dielectric layer is formed on the bottom electrode. A first top electrode layer is deposited on the dielectric layer by a first deposition process. A diffusion barrier layer is deposited on the first top electrode layer by a second deposition process different from the first deposition process. A second top electrode layer is deposited on the diffusion barrier layer by a third deposition. The third deposition process is the same as the first deposition process.
    Type: Grant
    Filed: July 19, 2022
    Date of Patent: March 25, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsing-Lien Lin, Chii-Ming Wu, Hai-Dang Trinh, Fa-Shen Jiang
  • Publication number: 20250081864
    Abstract: A semiconductor device includes a diffusion barrier structure, a bottom electrode, a top electrode, a switching layer and a capping layer. The bottom electrode is over the diffusion barrier structure. The top electrode is over the bottom electrode. The switching layer is between the bottom electrode and the top electrode, and configured to store data. The capping layer is between the switching layer and the top electrode. The diffusion barrier structure includes a multiple-layer structure. A thermal conductivity of the diffusion barrier structure is greater than approximately 20 W/mK.
    Type: Application
    Filed: November 18, 2024
    Publication date: March 6, 2025
    Inventors: HAI-DANG TRINH, FA-SHEN JIANG, HSING-LIEN LIN, CHII-MING WU
  • Patent number: 12245529
    Abstract: Some embodiments relate to a method for forming an integrated chip. The method includes forming a bottom electrode over a substrate. A data storage layer is formed on the bottom electrode. A diffusion barrier layer is formed over the data storage layer. The diffusion barrier layer has a first diffusion activation temperature. A top electrode is formed over the diffusion barrier layer. The top electrode has a second diffusion activation temperature less than the first diffusion activation temperature.
    Type: Grant
    Filed: July 31, 2023
    Date of Patent: March 4, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Albert Zhong, Cheng-Yuan Tsai, Hai-Dang Trinh, Shing-Chyang Pan
  • Patent number: 12239035
    Abstract: Various embodiments of the present disclosure are directed towards a method for forming a memory device. The method includes forming a bottom electrode over a substrate. A data storage structure is formed on the bottom electrode. The data storage structure comprises a first atomic percentage of a first dopant and a second atomic percentage of a second dopant. The first atomic percentage is different from the second atomic percentage. A top electrode is formed on the data storage structure.
    Type: Grant
    Filed: July 19, 2022
    Date of Patent: February 25, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hai-Dang Trinh, Chii-Ming Wu, Hsing-Lien Lin, Tzu-Chung Tsai, Fa-Shen Jiang, Bi-Shen Lee
  • Patent number: 12232434
    Abstract: Various embodiments of the present disclosure are directed towards a method for forming an integrated chip. The method includes forming a bottom electrode over a substrate. A data storage structure is formed on the bottom electrode. The data storage structure comprises a first dopant with a first atomic percent and a second dopant with a second atomic percent. The first atomic percent is different from the second atomic percent. A top electrode is formed on the data storage structure.
    Type: Grant
    Filed: June 30, 2022
    Date of Patent: February 18, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bi-Shen Lee, Hai-Dang Trinh, Fa-Shen Jiang, Hsun-Chung Kuang
  • Patent number: 12232336
    Abstract: A memory device includes a field effect transistor and a variable-capacitance capacitor. A gate structure includes a gate dielectric and an intermediate electrode. The variable-capacitance capacitor includes a lower capacitor plate comprising the intermediate electrode, an upper capacitor plate comprising a control gate electrode, and a variable-capacitance node dielectric and including an electrical-field-programmable metal oxide material. The electrical-field-programmable metal oxide material provides a variable effective dielectric constant, and a data bit may be stored as a dielectric state of the variable-capacitance node dielectric in the memory device. The variable-capacitance node dielectric provides reversible electrical field-dependent resistivity modulation, or reversible electrical field-dependent movement of metal atoms therein.
    Type: Grant
    Filed: November 10, 2023
    Date of Patent: February 18, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Fa-Shen Jiang, Hsia-Wei Chen, Hai-Dang Trinh, Hsun-Chung Kuang
  • Patent number: 12225834
    Abstract: A method for forming a semiconductor structure includes following operations. A first conductive layer is formed. A first dielectric layer is formed over the first conductive layer, and the first dielectric layer includes at least one trench exposing the first conductive layer. A second conductive layer is formed in the trench. A third conductive layer is formed in the trench, and a resistivity of the third conductive layer is greater than a resistivity of the second conductive layer. A second dielectric layer is formed over the third conductive layer. A phase change material is formed over the first dielectric layer.
    Type: Grant
    Filed: June 1, 2021
    Date of Patent: February 11, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Hsing-Lien Lin, Hai-Dang Trinh, Fa-Shen Jiang
  • Publication number: 20250048645
    Abstract: In some embodiments, the present disclosure relates to a memory device including a semiconductor substrate, a first electrode disposed over the semiconductor substrate, a ferroelectric layer disposed between the first electrode and the semiconductor substrate, and a first stressor layer separating the first electrode from the ferroelectric layer. The first stressor layer has a coefficient of thermal expansion greater than that of the ferroelectric layer.
    Type: Application
    Filed: October 23, 2024
    Publication date: February 6, 2025
    Inventors: Bi-Shen Lee, Tzu-Yu Lin, Yi-Yang Wei, Hai-Dang Trinh, Hsun-Chung Kuang, Cheng-Yuan Tsai
  • Publication number: 20250014984
    Abstract: In some implementations described herein, a capacitor structure may include a metal-insulator-metal structure in which work function metal layers are included between the insulator layer of the capacitor structure and the conductive electrode layers of the capacitor structure. The work function metal layers may enable high-k dielectric materials to be used for the insulator layer in that the work function metal layers may provide an increased electron barrier height between the insulator layer and the conductive electrode layers, which may increase the breakdown voltage and may reduce the current leakage for the capacitor structure.
    Type: Application
    Filed: July 3, 2023
    Publication date: January 9, 2025
    Inventors: Bi-Shen LEE, Chia-Hua LIN, Hai-Dang TRINH, Chung-Yi YU, Cheng-Yuan TSAI
  • Patent number: 12178147
    Abstract: A semiconductor device includes a diffusion barrier structure, a bottom electrode, a top electrode, a switching layer and a capping layer. The bottom electrode is over the diffusion barrier structure. The top electrode is over the bottom electrode. The switching layer is between the bottom electrode and the top electrode, and configured to store data. The capping layer is between the switching layer and the top electrode. The diffusion barrier structure includes a multiple-layer structure. A thermal conductivity of the diffusion barrier structure is greater than approximately 20 W/mK.
    Type: Grant
    Filed: October 16, 2022
    Date of Patent: December 24, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Hai-Dang Trinh, Fa-Shen Jiang, Hsing-Lien Lin, Chii-Ming Wu
  • Patent number: 12160995
    Abstract: In some embodiments, the present disclosure relates to a memory device including a semiconductor substrate, a first electrode disposed over the semiconductor substrate, a ferroelectric layer disposed between the first electrode and the semiconductor substrate, and a first stressor layer separating the first electrode from the ferroelectric layer. The first stressor layer has a coefficient of thermal expansion greater than that of the ferroelectric layer.
    Type: Grant
    Filed: June 26, 2023
    Date of Patent: December 3, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bi-Shen Lee, Tzu-Yu Lin, Yi-Yang Wei, Hai-Dang Trinh, Hsun-Chung Kuang, Cheng-Yuan Tsai
  • Publication number: 20240387578
    Abstract: An image sensor device is disclosed. The image sensor device includes: a substrate having a front surface and a back surface; two adjacent radiation-sensing regions formed in the substrate; and a trench isolation structure extending from the back surface of the substrate into the substrate between the two adjacent radiation-sensing regions. The trench isolation structure includes: a dielectric material; a first film being formed between the dielectric material and the substrate; a second film being formed between the first film and the dielectric material; and a third film being formed between the second film and the dielectric material. An electronegativity of the first film, an electronegativity of the second film and an electronegativity of the third film are different from each other.
    Type: Application
    Filed: July 30, 2024
    Publication date: November 21, 2024
    Inventors: CHIH-YU LAI, MIN-YING TSAI, YEUR-LUEN TU, HAI-DANG TRINH, CHENG-YUAN TSAI
  • Publication number: 20240381664
    Abstract: Ferroelectric stacks are disclosed herein that can improve retention performance of ferroelectric memory devices. An exemplary ferroelectric stack has a ferroelectric switching layer (FSL) stack disposed between a first electrode and a second electrode. The ferroelectric stack includes a barrier layer disposed between a first FSL and a second FSL, where a first crystalline condition of the barrier layer is different than a second crystalline condition of the first FSL and/or the second FSL. In some embodiments, the first crystalline condition is an amorphous phase, and the second crystalline condition is an orthorhombic phase. In some embodiments, the first FSL and/or the second FSL include a first metal oxide, and the barrier layer includes a second metal oxide. The ferroelectric stack can be a ferroelectric capacitor, a portion of a transistor, and/or connected to a transistor in a ferroelectric memory device to provide data storage in a non-volatile manner.
    Type: Application
    Filed: July 25, 2024
    Publication date: November 14, 2024
    Inventors: Yi Yang WEI, Tzu-Yu LIN, Bi-Shen LEE, Hai-Dang TRINH, Hsing-Lien LIN, Hsun-Chung KUANG
  • Publication number: 20240381663
    Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a lower electrode structure disposed over one or more interconnects. The one or more interconnects are arranged within a lower inter-level dielectric (ILD) structure over a substrate. A barrier is arranged along a lower surface of the lower electrode structure. The barrier separates the lower electrode structure from the one or more interconnects. An amorphous initiation layer is over the lower electrode structure and a ferroelectric material is on the amorphous initiation layer. The ferroelectric material has a substantially uniform orthorhombic crystalline phase. An upper electrode is over the ferroelectric material.
    Type: Application
    Filed: July 22, 2024
    Publication date: November 14, 2024
    Inventors: Bi-Shen Lee, Yi Yang Wei, Hai-Dang Trinh, Hsun-Chung Kuang, Cheng-Yuan Tsai
  • Publication number: 20240381793
    Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a bottom electrode over a substrate. A top electrode overlies the bottom electrode. A capping structure is disposed between the top electrode and the bottom electrode. The capping structure comprises a diffusion barrier layer vertically stacked with a metal layer. A switching structure is disposed between the bottom electrode and the capping structure. The switching structure comprises a dielectric layer on the bottom electrode and a first oxygen affinity layer on the dielectric layer. A first Gibbs free energy of the first oxygen affinity layer is less than a second Gibbs free energy of the dielectric layer. A first difference between the first Gibbs free energy and the second Gibbs free energy is less than ?100 kJ/mol.
    Type: Application
    Filed: January 29, 2024
    Publication date: November 14, 2024
    Inventors: Fa-Shen Jiang, Hai-Dang Trinh, Cheng-Yuan Tsai, Chung-Yi Yu
  • Publication number: 20240371907
    Abstract: Various embodiments of the present disclosure are directed towards an image sensor. The image sensor includes and image sensor element disposed within a substrate. The substrate comprises a first material. The image sensor element includes an active layer comprising a second material different from the first material. A buffer layer is disposed between the active layer and the substrate. The buffer layer extends along outer sidewalls and a bottom surface of the active layer. A capping structure overlies the active layer. Outer sidewalls of the active layer are spaced laterally between outer sidewalls of the capping structure such that the capping structure continuously extends over outer edges of the active layer.
    Type: Application
    Filed: July 18, 2024
    Publication date: November 7, 2024
    Inventors: Chun-Kai Lan, Hai-Dang Trinh, Hsun-Chung Kuang
  • Publication number: 20240373760
    Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) chip comprising a memory cell with a sidewall spacer, and/or an etch stop layer, doped to reduce charge accumulation at an interface between the sidewall spacer and the etch stop layer. The memory cell comprises a bottom electrode, a data storage element overlying the bottom electrode, and a top electrode overlying the data storage element. The sidewall spacer overlies the bottom electrode on a common sidewall formed by the data storage element and the top electrode, and the etch stop layer lines the sidewall spacer. The sidewall spacer and the etch stop layer directly contact at the interface and form an electric dipole at the interface. The doping to reduce charge accumulation reduces an electric field produced by the electric dipole, thereby reducing the effect of the electric field on the memory cell.
    Type: Application
    Filed: July 17, 2024
    Publication date: November 7, 2024
    Inventors: Bi-Shen Lee, Hai-Dang Trinh, Hsun-Chung Kuang, Cheng-Yuan Tsai