Patents by Inventor Haiyang Zhang

Haiyang Zhang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130075811
    Abstract: The present invention discloses a double gate transistor and a method of fabricating said transistor, said transistor comprising: a semiconductor layer on a substrate; a fin structure formed in said semiconductor layer, said fin structure having two end portions for forming source and drain regions and a middle portion between said two end portions for forming a channel region, said middle portion including two opposed side surfaces perpendicular to a substrate surface; a first gate dielectric layer and a first gate disposed on one side surface of said middle portion; and a second gate dielectric layer and a second gate disposed on the other side surface of said middle portion.
    Type: Application
    Filed: December 13, 2011
    Publication date: March 28, 2013
    Applicant: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventors: XINPENG WANG, Haiyang Zhang
  • Publication number: 20130073714
    Abstract: According to one embodiment of the present disclosure, a method for synchronizing data sets includes receiving a request to synchronize a first data set associated with a first server and a second data set associated with a second server. The method also includes determining, with reference to one or more replication constraints, whether to begin synchronization. The method further includes applying one or more resource control actions in response to determining to begin synchronization.
    Type: Application
    Filed: September 15, 2011
    Publication date: March 21, 2013
    Applicant: Computer Associates Think, Inc.
    Inventors: Xiaopin (Hector) Wang, Shisheng (Victor) Liu, Guoxian Shang, Haiyang Zhang
  • Publication number: 20130059438
    Abstract: A pattern formation method, mask pattern formation method and a method for manufacturing semiconductor devices are provided in this disclosure, which are directed to the field of semiconductor processes. The pattern formation method comprises: providing a substrate; forming a polymer thin film containing a block copolymer on the substrate; forming a first pattern through imprinting the polymer thin film with a stamp; forming domains composed of different copolymer components through directed self assembly of the copolymer in the first pattern; selectively removing the domains composed of copolymer components to form a second pattern. In the embodiments of the present invention, finer pitch patterns can be obtained through combining the imprinting and DSA process without exposure, which as compared to the prior art methods has the advantage of simplicity. Furthermore, stamps used in imprinting may have relative larger pitches, facilitating and simplifying the manufacture and alignment of the stamps.
    Type: Application
    Filed: November 10, 2011
    Publication date: March 7, 2013
    Applicant: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventors: JUNQING ZHOU, XIAOYING MENG, HAIYANG ZHANG
  • Publication number: 20130054529
    Abstract: Systems and methods for generating a bookmark for a snapshot of one or more volumes of a production server include initiating a snapshot process to capture a shadow copy of a snapshot-volume set, which includes one or more volumes of the production server. The snapshot process (e.g., Volume Shadow Copy Service of Windows™ operating system) may include (a) temporarily freezing operations on a file system of the production server, and (b) releasing a freeze of operations on the file system of the production server. A bookmark for the shadow copy (representing a consistent state of the associated volumes) may be generated such that the bookmark corresponds to a completion of the temporarily freezing or releasing a freeze of the operations. The bookmark may include a point in time of the completion of the temporarily freezing or releasing the freeze of the operations.
    Type: Application
    Filed: August 24, 2011
    Publication date: February 28, 2013
    Applicant: Computer Associates Think, Inc.
    Inventors: Xiaopin Wang, Haiyang Zhang, Shaorong Li
  • Patent number: 8377827
    Abstract: A method for forming a gate, which can improve the etching uniformity of the sidewalls of the gate, includes the following steps: forming a dielectric layer on a semiconductor substrate; forming a polysilicon layer on the dielectric layer; etching the polysilicon layer; performing an isotropic plasma etching process on the etched polysilicon layer by using a mixed gases containing a fluorine-based gas and oxygen gas; and cleaning the semiconductor substrate subjected to the isotropic plasma etching process, thereby forming a gate. The present invention further provides a method for forming a shallow trench isolation region, which can improve the filling quality of a subsequent spacer and the electrical properties of the resultant shallow trench isolation region, and a method for planarizing an etched surface of silicon substrate, which can improve the etching uniformity of the surface of silicon substrate.
    Type: Grant
    Filed: August 12, 2011
    Date of Patent: February 19, 2013
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Qiuhua Han, Haiyang Zhang, Qingtian Ma
  • Publication number: 20130034960
    Abstract: The present invention discloses a method of fabricating a semiconductor device. In the present invention, after the formation of a photo-resist mask on a substrate, the photo-resist is subjected to a plasma pre-treatment, and then etch is conducted. With the plasma pre-treatment, a line width roughness of a linear pattern of the photo-resist can be improved, and thus much better linear patterns can be formed on the substrate during the subsequent etching steps.
    Type: Application
    Filed: December 2, 2011
    Publication date: February 7, 2013
    Applicant: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventors: MINDA HU, DONGJIANG WANG, HAIYANG ZHANG
  • Publication number: 20130034964
    Abstract: The present invention discloses a method of manufacturing a semiconductor device. In order to form a trench with a smaller width, patterns of various monomers are formed by utilizing self-assembly characteristics of a block copolymer comprising various monomers. A metal or metal nitride is deposited on a surface of the block copolymer, the metal or metallic nitride selectively depositing due to a preferential chemical affinity between various monomers and the metal or metal nitride. After reaching a certain thickness, the metal or metal nitride layer begins to grow laterally. Deposition can be stopped by controlling deposition time so that the metal or metal nitride layer grows laterally but does not completely cover the surface of the block copolymer. Etching is then conducted using the metal or metal nitride layer as a mask to obtain a trench with a very small width.
    Type: Application
    Filed: December 12, 2011
    Publication date: February 7, 2013
    Applicant: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventors: HAIYANG ZHANG, MINDA HU
  • Patent number: 8367554
    Abstract: A method for forming a gate, which can improve the etching uniformity of the sidewalls of the gate, includes the following steps: forming a dielectric layer on a semiconductor substrate; forming a polysilicon layer on the dielectric layer; etching the polysilicon layer; performing an isotropic plasma etching process on the etched polysilicon layer by using a mixed gases containing a fluorine-based gas and oxygen gas; and cleaning the semiconductor substrate subjected to the isotropic plasma etching process, thereby forming a gate. The present invention further provides a method for forming a shallow trench isolation region, which can improve the filling quality of a subsequent spacer and the electrical properties of the resultant shallow trench isolation region, and a method for planarizing an etched surface of silicon substrate, which can improve the etching uniformity of the surface of silicon substrate.
    Type: Grant
    Filed: August 12, 2011
    Date of Patent: February 5, 2013
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Qiuhua Han, Haiyang Zhang, Qingtian Ma
  • Publication number: 20120326328
    Abstract: A method for manufacturing a semiconductor device includes providing a substrate having a first surface and a second surface, the second surface is on the opposite side of the substrate facing away from the first surface. The method further includes forming a first portion of an opening by etching a portion of the substrate from the first surface, forming a buffer layer on an inner surface of the first portion, etching a bottom of the buffer layer to expose an area of the underlying substrate, and etching the exposed area of the substrate to form a second portion of the opening. The method also includes performing an isotropic etching on the second portion of the opening to obtain a flask-shaped opening and filling the opening with a filling material. The method also includes partially removing a portion of the second surface and the filling material from the second portion of the opening.
    Type: Application
    Filed: November 8, 2011
    Publication date: December 27, 2012
    Applicant: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: FAN LI, Haiyang Zhang
  • Publication number: 20120286370
    Abstract: A semiconductor device and method for manufacturing the same are disclosed. The method comprises: forming a gate insulating layer and a gate above a substrate; forming a spacer on both sides of the gate respectively; etching the substrate with the gate and spacers as mask to form indents; respectively forming a dummy sidewall on the side of the spacers opposite to the gate; etching substrate with the gate, spacers and dummy sidewalls as mask to form recesses which are deeper than the indents; removing the dummy sidewalls; and filling SiGe in the indents and recesses to form source/drain extent regions and source/drain regions of the semiconductor device; wherein before the step of filling SiGe, a step of heating the substrate to reflow the substrate material so as to at least change the shape of the side surface of the indent on the side close to the gate is implemented.
    Type: Application
    Filed: September 23, 2011
    Publication date: November 15, 2012
    Applicant: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventors: FAN LI, Haiyang Zhang
  • Publication number: 20120289017
    Abstract: A method of manufacturing a semiconductor device comprises placing a semiconductor substrate in an ashing chamber, the semiconductor substrate having a gate, a silicon nitride gate sidewall offset spacer or a silicon nitride gate sidewall pacer formed thereon, and a photo resist residue remaining on the semiconductor substrate, introducing a gas mixture including D2 or T2 into the ashing chamber, and ashing the photo resist residue using a plasma that is formed from the gas mixture. The gas mixture can include a deuterium gas or a tritium gas having a volume ratio ranging between about 1% and about 20%. Embodiments can reduce Si recess and the loss of silicon nitride thin film during ashing.
    Type: Application
    Filed: December 14, 2011
    Publication date: November 15, 2012
    Applicant: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: XIAOYING MENG, Junqing Zhou, Haiyang Zhang
  • Publication number: 20120276737
    Abstract: A method for post-etching treatment of copper interconnecting wires that are used to electrically couple an upper interconnecting layer with a lower interconnecting layer includes forming the lower interconnecting layer on a substrate, and forming the upper interconnecting layer on the lower interconnecting layer. The lower interconnecting layer includes a first dielectric layer, a plurality of wire trenches formed in the first dielectric layer and being filled with copper, and a first top barrier layer overlying the first dielectric layer and the wire trenches. The upper interconnecting layer includes a second dielectric layer on the top barrier layer, and a plurality of vias extending through the second dielectric layer and the top barrier layer and exposing the copper in the wire trenches. The method further includes treating the exposed copper using a plasma process comprising NH3.
    Type: Application
    Filed: November 23, 2011
    Publication date: November 1, 2012
    Applicant: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: DONGJIANG WANG, Junqing Zhou, Haiyang Zhang
  • Publication number: 20120273923
    Abstract: A method of manufacturing semiconductor device and a wafer are provided in accordance with embodiments of the present invention, which relates to semiconductor technology. The method includes: providing a substrate, and forming a gate oxide layer and a polysilicon layer on a first surface of the substrate; etching the polysilicon layer by use of a patterned mask so as to form a polysilicon gate with reentrants; depositing a tensile stress film on a second surface of the substrate before etching the polysilicon layer. The tensile stress film can be deposited on the second surface of the substrate for generating the tensile stress for the wafer. Thus, a polysilicon gate with reentrants can be formed in etching process. In this way, semiconductor devices can have smaller gate-source/drain overlap capacitance and better TDDB parameters, and the performance of the devices can be improved.
    Type: Application
    Filed: September 23, 2011
    Publication date: November 1, 2012
    Applicant: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventors: Xiaoying Meng, Junqing Zhou, Haiyang Zhang
  • Publication number: 20120197844
    Abstract: Systems and methods for replicating data from a production server to a backup server include identifying one or more data blocks of a file that were modified after a first time instant and before a second time instant. The file may be associated with a protected directory of the production server. An representative data block (e.g., including a hash value) for at least one of the identified data blocks may be computed using a cryptography algorithm, e.g., MD5 or SHA-1. The computed cryptographic data block representing the identified data block may then be sent for replication to the backup server. An operation performed between the first time instant and the second time instant on one or more files of the protected directory may be recorded, and sent to the backup server.
    Type: Application
    Filed: February 1, 2011
    Publication date: August 2, 2012
    Applicant: Computer Associates Think, Inc.
    Inventors: Hector Wang, Haiyang Zhang, Shaorong Li, Guoxian Shang
  • Publication number: 20120136827
    Abstract: Systems and methods for replicating data from a production server to a backup server include recording at least one operation on one or more data items stored in a volume of a production server. The operation may be recorded as at least one journal event in a memory. A determination may then be made regarding whether a system malfunction incident has occurred in the production server and if so, a first set of journal events may be transferred from the memory to an auxiliary storage at a first time instant. At a second time instant, a second set of journal events recorded in the memory between the first and second time instants may be transferred to the auxiliary storage. At one journal event stored in the auxiliary storage unit may then be sent for replication to a backup server.
    Type: Application
    Filed: November 29, 2010
    Publication date: May 31, 2012
    Applicant: Computer Associates Think, Inc.
    Inventors: Xiaopin Wang, Haiyang Zhang, Shaorong Li
  • Publication number: 20110300688
    Abstract: A method for forming a gate, which can improve the etching uniformity of the sidewalls of the gate, includes the following steps: forming a dielectric layer on a semiconductor substrate; forming a polysilicon layer on the dielectric layer; etching the polysilicon layer; performing an isotropic plasma etching process on the etched polysilicon layer by using a mixed gases containing a fluorine-based gas and oxygen gas; and cleaning the semiconductor substrate subjected to the isotropic plasma etching process, thereby forming a gate. The present invention further provides a method for forming a shallow trench isolation region, which can improve the filling quality of a subsequent spacer and the electrical properties of the resultant shallow trench isolation region, and a method for planarizing an etched surface of silicon substrate, which can improve the etching uniformity of the surface of silicon substrate.
    Type: Application
    Filed: August 12, 2011
    Publication date: December 8, 2011
    Applicant: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Qiuhua Han, Haiyang Zhang, Qingtian Ma
  • Publication number: 20110300698
    Abstract: A method for forming a gate, which can improve the etching uniformity of the sidewalls of the gate, includes the following steps: forming a dielectric layer on a semiconductor substrate; forming a polysilicon layer on the dielectric layer; etching the polysilicon layer; performing an isotropic plasma etching process on the etched polysilicon layer by using a mixed gases containing a fluorine-based gas and oxygen gas; and cleaning the semiconductor substrate subjected to the isotropic plasma etching process, thereby forming a gate. The present invention further provides a method for forming a shallow trench isolation region, which can improve the filling quality of a subsequent spacer and the electrical properties of the resultant shallow trench isolation region, and a method for planarizing an etched surface of silicon substrate, which can improve the etching uniformity of the surface of silicon substrate.
    Type: Application
    Filed: August 12, 2011
    Publication date: December 8, 2011
    Applicant: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Qiuhua Han, Haiyang Zhang, Qingtian Ma
  • Publication number: 20110282843
    Abstract: A work flow is initiated and identified by a scenario identifier. A file system driver is notified to record operations on data associated with the work flow identified by the scenario identifier as raw journals without recording data content associated with the operations. The recorded operations are consolidated with previous operations as each operation is recorded in the raw journals. A system snapshot is initiated to be taken. The file system driver is notified of a point in time the system snapshot is taken. Data content associated with the consolidated recorded operations is retrieved from the system snapshot. A first packet is created from selected recorded operations and sent synchronously. A second packet including rest of the recorded operations along with associated data content are sent asynchronously with the point in time of the system snapshot.
    Type: Application
    Filed: May 17, 2010
    Publication date: November 17, 2011
    Applicant: COMPUTER ASSOCIATES THINK, INC.
    Inventors: Xiaopin (Hector) Wang, Haiyang Zhang, Shaorong Li
  • Publication number: 20110276573
    Abstract: Journal event consolidation extracts events occurring between two predetermined point in time on data volume, categorizes the events into categories of events, and consolidates the events in the categories of events.
    Type: Application
    Filed: May 6, 2010
    Publication date: November 10, 2011
    Applicant: COMPUTER ASSOCIATES THINK, INC.
    Inventors: Xiaopin (Hector) Wang, Haiyang Zhang, Shaorong Li
  • Patent number: 8039402
    Abstract: There is provide a method for forming a gate, which can improve the etching uniformity of the sidewalls of the gate, including the following steps: forming a dielectric layer on a semiconductor substrate; forming a polysilicon layer on the dielectric layer; etching the polysilicon layer; performing an isotropic plasma etching process on the etched polysilicon layer by using a mixed gases containing a fluorine-based gas and oxygen gas; and cleaning the semiconductor substrate subjected to the isotropic plasma etching process, thereby forming a gate. there are also provided a method for forming a shallow trench isolation region, which can improve the filling quality of a subsequent spacer and the electrical properties of the resultant shallow trench isolation region by improving the etching uniformity of sidewalls and bottom surface of the shallow trench, and a method for planarizating an etched surface of silicon substrate, which can improve the etching uniformity of the surface of silicon substrate.
    Type: Grant
    Filed: December 11, 2008
    Date of Patent: October 18, 2011
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Qiuhua Han, Haiyang Zhang, Qingtian Ma