Patents by Inventor Haiyang Zhang

Haiyang Zhang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170221754
    Abstract: An apparatus includes a housing, a chamber disposed in the housing and configured to receive a substrate, a shower head disposed outside the housing and configured to supply a process gas to the chamber, and a hot wire at a first temperature disposed between the shower head and the substrate. The hot wire at the first temperature ionizes the process gas, and the ionized gas is supplied to the substrate for performing a hot-wire assisted plasma-assisted pre-cleaning process and a hot-wire assisted atomic layer deposition process. The apparatus also includes a hot plate in the chamber and configured to bring the substrate to a second temperature.
    Type: Application
    Filed: January 9, 2017
    Publication date: August 3, 2017
    Inventors: GUANGJIE YUAN, JUNQING ZHOU, HAIYANG ZHANG
  • Publication number: 20170161161
    Abstract: Systems and methods for replicating data from a production server to a backup server include recording at least one operation on one or more data items stored in a volume of a production server. The operation may be recorded as at least one journal event in a memory. A determination may then be made regarding whether a system malfunction incident has occurred in the production server and if so, a first set of journal events may be transferred from the memory to an auxiliary storage at a first time instant. At a second time instant, a second set of journal events recorded in the memory between the first and second time instants may be transferred to the auxiliary storage. At one journal event stored in the auxiliary storage unit may then be sent for replication to a backup server.
    Type: Application
    Filed: February 22, 2017
    Publication date: June 8, 2017
    Inventors: Xiaopin WANG, Haiyang Zhang, Shaorong Li
  • Patent number: 9613880
    Abstract: A method for fabricating a semiconductor structure includes: providing a substrate with a dielectric layer and a passivation layer formed on the substrate; forming a via through the dielectric layer and exposing the substrate; forming a first conductive layer to fill the via with a top surface of the first conductive layer leveled with a top surface of the passivation layer; forming a patterned layer with an opening on the passivation layer. The opening is located above the first conductive layer with a dimension larger than the dimension of the via. The method also includes forming a trench in the dielectric layer; forming a second conductive layer to fill the trench and to electrically connect to the first conductive layer; then removing a portion of the second conductive layer, the patterned layer, and the passivation layer to make a top surface of the second conductive layer level with a top surface of the dielectric layer.
    Type: Grant
    Filed: December 3, 2015
    Date of Patent: April 4, 2017
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventors: Chenglong Zhang, Haiyang Zhang
  • Publication number: 20170084747
    Abstract: A method for fabricating a FinFET structure comprises providing a semiconductor substrate; forming a hard mask layer on the semiconductor substrate; forming a dummy gate structure having a dummy gate, a first sidewall spacer and a second sidewall spacer; removing the dummy gate to form a first trench; forming first sub-fins in the semiconductor substrate under the hard mask layer in the first trench; forming a first metal gate structure in the first trench; removing the first sidewall spacer to form a second trench; forming second sub-fins in the semiconductor substrate under the hard mask layer in the second trench; forming a second metal gate structure in the second trench; removing the second sidewall spacer to form a third trench; forming third sub-fins in the semiconductor substrate under the hard mask layer in the third trench; and forming a third metal gate structure in the third trench.
    Type: Application
    Filed: December 5, 2016
    Publication date: March 23, 2017
    Inventors: HAIYANG ZHANG, CHENGLONG ZHANG
  • Patent number: 9588858
    Abstract: Systems and methods for replicating data from a production server to a backup server include recording at least one operation on one or more data items stored in a volume of a production server. The operation may be recorded as at least one journal event in a memory. A determination may then be made regarding whether a system malfunction incident has occurred in the production server and if so, a first set of journal events may be transferred from the memory to an auxiliary storage at a first time instant. At a second time instant, a second set of journal events recorded in the memory between the first and second time instants may be transferred to the auxiliary storage. At one journal event stored in the auxiliary storage unit may then be sent for replication to a backup server.
    Type: Grant
    Filed: November 29, 2010
    Date of Patent: March 7, 2017
    Assignee: CA, Inc.
    Inventors: Xiaopin Wang, Haiyang Zhang, Shaorong Li
  • Publication number: 20170062571
    Abstract: The disclosed subject matter provides a Fin-FET with a thinned-down InP layer and thinning-down method thereof. In a Fin-FET, the fin structure is made of InGaAs and an InP layer is formed to cover the fin structure. The InP layer is obtained from an initial InP layer formed on the fin structure through a thinning down process including converting a surface portion of the InP layer into a Phosphor-rich layer and removing the Phosphor-rich layer. The thickness of the ultimately-formed InP layer is less than or equal to 1 nm. According to the disclosed method, the InP layer in the Fin-FET may be easily thinned down, and during the thinning-down process, contamination may be avoided.
    Type: Application
    Filed: August 12, 2016
    Publication date: March 2, 2017
    Inventors: HAIYANG ZHANG, CHENGLONG ZHANG
  • Patent number: 9564512
    Abstract: A method for fabricating a FinFET structure comprises providing a semiconductor substrate; forming a hard mask layer on the semiconductor substrate; forming a dummy gate structure having a dummy gate, a first sidewall spacer and a second sidewall spacer; removing the dummy gate to form a first trench; forming first sub-fins in the semiconductor substrate under the hard mask layer in the first trench; forming a first metal gate structure in the first trench; removing the first sidewall spacer to form a second trench; forming second sub-fins in the semiconductor substrate under the hard mask layer in the second trench; forming a second metal gate structure in the second trench; removing the second sidewall spacer to form a third trench; forming third sub-fins in the semiconductor substrate under the hard mask layer in the third trench; and forming a third metal gate structure in the third trench.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: February 7, 2017
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventors: Haiyang Zhang, Chenglong Zhang
  • Patent number: 9537739
    Abstract: A method implemented by a node in a high availability system having a master node and a replica node, the method including monitoring another node to determine whether or not the node is responding via a network connection, when the node is found to be not responding, changing into a periodic replication mode of operation, serving user requests while in the replication mode of operation, determining that the other node is now responding via the network connection, negotiating to merge changes resulting from serving the user requests with the other node, and reverting to an online replication mode of operation.
    Type: Grant
    Filed: July 16, 2013
    Date of Patent: January 3, 2017
    Assignee: CA, Inc.
    Inventors: Xiaopin Wang, Haiyang Zhang, Shishen Liu, Guoxian Shang
  • Patent number: 9529810
    Abstract: Synchronizing hard link files on master and replica servers includes providing master and replica server hard link file snapshots. The master server hard link file snapshot includes a listing of hard link file names from a root directory of the master server. The replica server hard link file snapshot includes a listing of hard link file names from a root directory of the replica server. The master server hard link file snapshot and the replica server hard link file snapshot are compared. A synchronized hash map linked list may be generated responsive to the comparison. The synchronized hash map linked list includes a listing of group identifications corresponding to physical data files at the master server. For each group identification in the synchronized hash map linked list, the synchronized hash map linked list includes at least a hard link file name from the root directory of the master server.
    Type: Grant
    Filed: February 18, 2014
    Date of Patent: December 27, 2016
    Assignee: CA, Inc.
    Inventors: Gongjun Fei, Haiyang Zhang, Shaorong Li
  • Patent number: 9524933
    Abstract: A method for forming a semiconductor structure including providing a substrate; forming a dielectric layer covering a surface of the substrate; forming a plurality of first through holes exposing the surface of the substrate by etching the dielectric layer; forming first conductive vias by filling the plurality of first through holes using a first metal material and first conductive lines on the first conductive vias also using the first metal material; forming a plurality of second through holes exposing the surface of the substrate by etching the dielectric layer; and forming second conductive vias by filling the plurality of second through holes using a second metal material, different from the first metal material, and second conductive lines over the second conductive vias also using the second metal material, wherein the second metal material has a different anti-electromigration ability from the first metal material.
    Type: Grant
    Filed: September 9, 2015
    Date of Patent: December 20, 2016
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventors: Haiyang Zhang, Chenglong Zhang
  • Patent number: 9489392
    Abstract: A data replication system and method is disclosed in which a master file server uses a first filter in a kernel space to intercept file I/O events, send the file I/O events over a first network, for example a local area network, to a second filter in a kernel space of a first replica file server, and submit the file I/O event to a file system program in user space of the master file server to be processed. The second filter records the file I/O event in a memory of the second file server and sends an acknowledge message to the first filter indicating the file I/O event received by the second filter has been recorded in the replica file server. The first filter notifies user land in the first file server that the file I/O event has been processed if the first filter has received the acknowledge message and the file system program has completed processing the file I/O event in the first file server.
    Type: Grant
    Filed: January 24, 2014
    Date of Patent: November 8, 2016
    Assignee: CA, Inc.
    Inventors: Xiaopin Wang, Haiyang Zhang, Guoxian Shang, Shaorong Li
  • Publication number: 20160293727
    Abstract: A method for fabricating a FinFET structure comprises providing a semiconductor substrate; forming a hard mask layer on the semiconductor substrate; forming a dummy gate structure having a dummy gate, a first sidewall spacer and a second sidewall spacer; removing the dummy gate to form a first trench; forming first sub-fins in the semiconductor substrate under the hard mask layer in the first trench; forming a first metal gate structure in the first trench; removing the first sidewall spacer to form a second trench; forming second sub-fins in the semiconductor substrate under the hard mask layer in the second trench; forming a second metal gate structure in the second trench; removing the second sidewall spacer to form a third trench; forming third sub-fins in the semiconductor substrate under the hard mask layer in the third trench; and forming a third metal gate structure in the third trench.
    Type: Application
    Filed: March 3, 2016
    Publication date: October 6, 2016
    Inventors: HAIYANG ZHANG, CHENGLONG ZHANG
  • Patent number: 9459883
    Abstract: A method includes identifying a first boot configuration type for a disk image. The disk image includes a master boot record and a disk partition. The disk partition comprises a volume boot record. The master boot record comprises first instructions for loading an operating system, and the volume boot record comprises second instructions for loading the operating system. The method further includes receiving an input indicative of a second boot configuration type. The method also includes modifying the disk image to use the second boot configuration type to load the operating system by modifying the first instructions and the second instructions.
    Type: Grant
    Filed: March 6, 2014
    Date of Patent: October 4, 2016
    Assignee: CA, Inc.
    Inventors: Haiyang Zhang, Xiaopin Wang, Victor Liu, Shaorong Li
  • Patent number: 9461172
    Abstract: Methods for fabricating semiconductor devices are provided. Gate structures are formed on a top surface of a substrate to form semiconductor devices. Trenches are formed in the substrate on both sides of each gate structure of each semiconductor device. The trenches on the both sides of each gate structure are filled with stress layers, the stress layers in the substrate protruding over the top surface of the substrate. The stress layers are ion-doped and annealed on the both sides of each gate structure, and are pulse-etched to form a source region and a drain region of each gate structure. The pulse-etching is controlled such that the source regions and the drain regions of the plurality of semiconductor devices have a top surface coplanar with the top surface of the substrate.
    Type: Grant
    Filed: October 21, 2014
    Date of Patent: October 4, 2016
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL CORPORATION
    Inventors: Haiyang Zhang, Jia Ren
  • Publication number: 20160284594
    Abstract: A method for forming a semiconductor structure includes providing a semiconductor substrate; forming a plurality of fins on the semiconductor substrate; forming a plurality of gate structures on the plurality of fins and sidewall spacers on side surfaces of the gate structures; forming a first dielectric layer on the semiconductor substrate; recessing the gate structures to form a plurality of trenches on top surfaces of the gate structures; forming a mask material layer filling the trenches and on the first dielectric layer; forming a protective layer on the top surfaces of the remaining gate structures and a mask layer on a portion of the first dielectric layer between adjacent gate structures by etching the mask material layer; forming contact through-holes in the first dielectric layer between adjacent gates structure at both sides of the mask layer; and forming a metal contact via in each of the contact through-holes.
    Type: Application
    Filed: March 3, 2016
    Publication date: September 29, 2016
    Inventors: CHENGLONG ZHANG, HAIYANG ZHANG
  • Publication number: 20160276283
    Abstract: The disclosed subject matter provides a semiconductor structure and fabrication method thereof. In a semiconductor structure, a dielectric layer, a plurality of discrete gate structures, and a plurality of sidewall spacers are formed on a semiconductor substrate. The plurality of discrete gate structures and sidewall spacers are formed in the dielectric layer, and a sidewall spacer is formed on each side of each gate structure. A top portion of each gate structure and a top portion of the dielectric layer between neighboring sidewall spacers of neighboring gate structures are removed. A protective layer is formed on each of the remaining dielectric layer and the remaining gate structures. Contact holes are formed on the semiconductor substrate, between neighboring sidewall spacers, and on opposite sides of the protective layer on the remaining dielectric layer. A metal plug is formed in each contact hole.
    Type: Application
    Filed: March 3, 2016
    Publication date: September 22, 2016
    Inventors: CHENGLONG ZHANG, HAIYANG ZHANG
  • Patent number: 9438468
    Abstract: Embodiments of the present invention provide a method for creating network devices, where the method includes: creating multiple virtual hardware systems of control planes on a hardware system of a control plane of a physical network device; creating multiple virtual hardware systems of forwarding planes on a hardware system of a forwarding plane of the physical network device; loading multiple software systems of the control planes to the multiple virtual hardware systems of the control planes, respectively; loading multiple software systems of the forwarding planes to the multiple virtual hardware systems of the forwarding planes, respectively; creating multiple communication channels. In addition, a corresponding apparatus also provided. By using the technical solutions provided by the embodiments of the present invention, multiple virtual network devices can run software systems in different versions.
    Type: Grant
    Filed: July 17, 2013
    Date of Patent: September 6, 2016
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Yinben Xia, Haiyang Zhang, Yuhong Yang
  • Patent number: 9410233
    Abstract: A method of manufacturing semiconductor device and a wafer are provided in accordance with embodiments of the present invention, which relates to semiconductor technology. The method includes: providing a substrate, and forming a gate oxide layer and a polysilicon layer on a first surface of the substrate; etching the polysilicon layer by use of a patterned mask so as to form a polysilicon gate with reentrants; depositing a tensile stress film on a second surface of the substrate before etching the polysilicon layer. The tensile stress film can be deposited on the second surface of the substrate for generating the tensile stress for the wafer. Thus, a polysilicon gate with reentrants can be formed in etching process. In this way, semiconductor devices can have smaller gate-source/drain overlap capacitance and better TDDB parameters, and the performance of the devices can be improved.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: August 9, 2016
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventors: Xiaoying Meng, Junqing Zhou, Haiyang Zhang
  • Patent number: 9380081
    Abstract: A system and method establishes bidirectional contact through firewall devices. A method includes establishing a first connection between a first device and a second device and storing a connection record on the second device. When the second device receives a request to connect with the first device, it identifies and searches for the connection record corresponding to the first device. When the second device finds the connection, the second device sends a request to establish a second connection from the second device to the first device. Upon receiving the request to establish a second connection, the first device verifies the request to establish the second connection and the lifetime of the first connection. Upon verification, the first device establishes the second connection between the first computing device and the second device.
    Type: Grant
    Filed: May 17, 2013
    Date of Patent: June 28, 2016
    Assignee: CA, Inc.
    Inventors: Guoxian Shang, Haiyang Zhang, Hector Wang, Raymond Huang, Alexey Shvechkov
  • Patent number: 9368409
    Abstract: The present disclosure provides a method for fabricating semiconductor devices. The method includes providing a substrate with a gate electrode film on the substrate and a gate electrode pattern film on the gate electrode film; forming at least one pattern layer on the gate electrode pattern film; and using the at least one pattern layer as the etch mask to etch portions of the gate electrode pattern film to expose portions of the gate electrode film and form a gate electrode pattern layer on the gate electrode film, the gate electrode pattern layer including a hard mask layer and a silicon layer, and sidewalls of the silicon layer in a direction perpendicular to a first direction having a first poly line width roughness. The method also includes performing an etch-repairing treatment on the sidewalls of the silicon layer in the direction perpendicular to the first direction.
    Type: Grant
    Filed: September 9, 2015
    Date of Patent: June 14, 2016
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventors: Haiyang Zhang, Xuan Zhang