Patents by Inventor Haiyang Zhang

Haiyang Zhang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160118338
    Abstract: A method for forming a semiconductor structure including providing a substrate; forming a dielectric layer covering a surface of the substrate; forming a plurality of first through holes exposing the surface of the substrate by etching the dielectric layer; forming first conductive vias by filling the plurality of first through holes using a first metal material and first conductive lines on the first conductive vias also using the first metal material; forming a plurality of second through holes exposing the surface of the substrate by etching the dielectric layer; and forming second conductive vias by filling the plurality of second through holes using a second metal material, different from the first metal material, and second conductive lines over the second conductive vias also using the second metal material, wherein the second metal material has a different anti-electromigration ability from the first metal material.
    Type: Application
    Filed: September 9, 2015
    Publication date: April 28, 2016
    Inventors: HAIYANG ZHANG, CHENGLONG ZHANG
  • Publication number: 20160111368
    Abstract: A method is provided for fabricating a semiconductor structure. The method includes providing a semiconductor substrate; forming an initial metal layer; simultaneously forming a plurality of discrete first metal layers and openings by etching the initial metal layer; forming a plurality of sidewalls covering the side surface of the first metal layers; and forming a plurality of second metal layers to fill the openings.
    Type: Application
    Filed: October 16, 2015
    Publication date: April 21, 2016
    Inventors: CHENGLONG ZHANG, HAIYANG ZHANG
  • Publication number: 20160111329
    Abstract: A method for forming an interconnect structure is provided. The method includes providing a substrate with a surface; and forming a metal layer covering the surface of the substrate and with a desired grain size to reduce grain boundary scattering of the interconnect structure subsequently formed with the metal layer. The method also includes etching the metal layer to form a plurality of metal lines on the surface of the substrate and a plurality of metal pillars on each of the plurality of the metal lines of the interconnect structure; and forming a dielectric layer covering the surface of the substrate, surfaces of the metal lines, and side surfaces of the metal pillars.
    Type: Application
    Filed: October 14, 2015
    Publication date: April 21, 2016
    Inventors: CHENGLONG ZHANG, HAIYANG ZHANG
  • Publication number: 20160086857
    Abstract: The present disclosure provides a method for fabricating semiconductor devices. The method includes providing a substrate with a gate electrode film on the substrate and a gate electrode pattern film on the gate electrode film; forming at least one pattern layer on the gate electrode pattern film; and using the at least one pattern layer as the etch mask to etch portions of the gate electrode pattern film to expose portions of the gate electrode film and form a gate electrode pattern layer on the gate electrode film, the gate electrode pattern layer including a hard mask layer and a silicon layer, and sidewalls of the silicon layer in a direction perpendicular to a first direction having a first poly line width roughness. The method also includes performing an etch-repairing treatment on the sidewalls of the silicon layer in the direction perpendicular to the first direction.
    Type: Application
    Filed: September 9, 2015
    Publication date: March 24, 2016
    Inventors: HAIYANG ZHANG, XUAN ZHANG
  • Publication number: 20160087075
    Abstract: The present disclosure provides a transistor device and fabrication method thereof. A dummy gate is formed on a substrate. An interlayer dielectric layer is formed on the substrate and sidewall surfaces of the dummy gate. The interlayer dielectric layer has a top surface coplanar with a top surface of the dummy gate. A mask layer is formed on the top surface of the interlayer dielectric layer. The mask layer is used as an etch mask to remove the dummy gate to form a trench in the interlayer dielectric layer to provide a trench footing on sidewall surfaces of the trench and near a trench bottom. The trench footing is then removed by applying a dry etching process. A gate electrode is then formed in the trench to form a transistor with improved electrical performance.
    Type: Application
    Filed: September 10, 2015
    Publication date: March 24, 2016
    Inventors: HAIYANG ZHANG, XUAN ZHANG
  • Patent number: 9286093
    Abstract: Various embodiments illustrated and described herein include systems, methods, and computer program products to set up network adaptors in a virtual machine. In some embodiments, a replica virtual machine is started when a replica server takes over for a failed master server. In some embodiments, prior to, or contemporaneously with, a switchover from the master server to the replica server, a virtual storage device of the replica virtual machine is mounted outside the virtual machine environment (e.g., not to the virtual machine). Network adaptor configuration information is copied to the virtual storage device. An injector tool is also configured to run automatically when the replica virtual machine is started. The virtual storage device is the unmounted. When the virtual machine is started as part of the switchover process, the injector tool runs and uses the network adaptor configuration information to configure the network adaptor.
    Type: Grant
    Filed: May 10, 2013
    Date of Patent: March 15, 2016
    Assignee: CA, Inc.
    Inventors: Jinxing Yin, Jiaolin Yang, Haiyang Zhang, Guoxian Shang
  • Patent number: 9268576
    Abstract: A method includes replicating data stored on storage devices of a physical master computer system to replica virtual storage devices via a network connection, modifying boot configuration data on the replica virtual storage devices to boot a physical replica computer system, and booting the physical replica computer system from the replica virtual storage devices to replace the physical master computer.
    Type: Grant
    Filed: May 8, 2013
    Date of Patent: February 23, 2016
    Assignee: CA, INC.
    Inventors: Haiyang Zhang, Shishen Liu, Lei Huang, Lei Wang
  • Patent number: 9244928
    Abstract: A system and method creates a directory snapshot. The method includes retrieving a group of filenames from a directory, splitting the group of filenames into a first plurality of filenames and a second plurality of filenames, and storing the first plurality of filenames into a first temporary snapshot file and storing the second plurality of filenames into a second temporary snapshot file. The filenames in the first and second temporary snapshot files are sorted based on the same heuristic and a sorted linked list that includes a filename listed first in the first temporary snapshot file and a filename listed first in the second temporary snapshot file is created. A first filename from the sorted linked list is saved to a result directory snapshot file.
    Type: Grant
    Filed: March 5, 2013
    Date of Patent: January 26, 2016
    Assignee: CA, Inc.
    Inventors: Haiyang Zhang, Guoxian Shang, Shaorong Li, Guodong Li
  • Patent number: 9239869
    Abstract: Various embodiments illustrated and described herein include systems, methods, and computer program products to protect NTFS deduplicated volumes. Some embodiments select a data protection mode from various modes to protect deduplicated volumes. Some data protection modes retrieve the deduplicated files and associated data chunks without rehydrating the files and send them to a replica. Some data protection modes rehydrate deduplicated files as they are retrieved, send the rehydrated files to the replica, and turn on deduplication at the replica so the files can be deduplicated on the replica. Deduplication settings can also be transferred to the replica so that deduplication on the replica mimics deduplication on the source. Some data protection modes replicate the deduplicated files to the replica.
    Type: Grant
    Filed: May 8, 2013
    Date of Patent: January 19, 2016
    Assignee: CA, Inc.
    Inventors: Haiyang Zhang, Gong jun Fei, Guoxian Shang, Shaorong Li
  • Patent number: 9239870
    Abstract: A database is automatically configured for recovery. Operating system compatibility, system recovery compatibility, and database server compatibility is verified. If the system recovery configuration is not compatible, then the system recovery configuration is updated. If the database server configuration is not compatible, then the database server configuration is updated.
    Type: Grant
    Filed: May 8, 2013
    Date of Patent: January 19, 2016
    Assignee: CA, Inc.
    Inventors: Guoxian Shang, Guodong Li, Haiyang Zhang
  • Publication number: 20150254080
    Abstract: A method includes identifying a first boot configuration type for a disk image. The disk image includes a master boot record and a disk partition. The disk partition comprises a volume boot record. The master boot record comprises first instructions for loading an operating system, and the volume boot record comprises second instructions for loading the operating system. The method further includes receiving an input indicative of a second boot configuration type. The method also includes modifying the disk image to use the second boot configuration type to load the operating system by modifying the first instructions and the second instructions.
    Type: Application
    Filed: March 6, 2014
    Publication date: September 10, 2015
    Applicant: CA, INC.
    Inventors: Haiyang Zhang, Xiaopin Wang, Victor Liu, Shaorong Li
  • Publication number: 20150234712
    Abstract: Synchronizing hard link files on master and replica servers includes providing master and replica server hard link file snapshots. The master server hard link file snapshot includes a listing of hard link file names from a root directory of the master server. The replica server hard link file snapshot includes a listing of hard link file names from a root directory of the replica server. The master server hard link file snapshot and the replica server hard link file snapshot are compared. A synchronized hash map linked list may be generated responsive to the comparison. The synchronized hash map linked list includes a listing of group identifications corresponding to physical data files at the master server. For each group identification in the synchronized hash map linked list, the synchronized hash map linked list includes at least a hard link file name from the root directory of the master server.
    Type: Application
    Filed: February 18, 2014
    Publication date: August 20, 2015
    Applicant: CA, INC.
    Inventors: Gongjun Fei, Haiyang Zhang, Shaorong Li
  • Publication number: 20150213051
    Abstract: A data replication system and method is disclosed in which a master file server uses a first filter in a kernel space to intercept a file I/O events, send the file I/O events over a first network, for example a local area network, to a second filter in a kernel space of a first replica file server, and submit the file I/O event to a file system program in user space of the master file server to be processed. The second filter records the file I/O event in a memory of the second file server and sends an acknowledge message to the first filter indicating the file I/O event received by the second filter has been recorded in the replica file server. The first filter notifies user land in the first file server that the file I/O event has been processed if the first filter has received the acknowledge message and the file system program has completed processing the file I/O event in the first file server.
    Type: Application
    Filed: January 24, 2014
    Publication date: July 30, 2015
    Applicant: CA, Inc.
    Inventors: Xiaopin Wang, Haiyang Zhang, Guoxian Shang, Shaorong Li
  • Patent number: 9087788
    Abstract: Various embodiments provide shallow trenches and fabrication methods. In an exemplary method, a semiconductor substrate can be provided. A mask layer can be provided on the semiconductor substrate. An etch-cleaning process can be performed. The etch-cleaning process can include etching the semiconductor substrate to form a shallow trench by one or more etching steps using the mask layer as an etch mask. The etch-cleaning process can further include performing a plasma cleaning process after each of the one or more etching steps. The plasma cleaning process can use a plasma that is electronegative.
    Type: Grant
    Filed: October 17, 2013
    Date of Patent: July 21, 2015
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventors: Haiyang Zhang, Dongjiang Wang
  • Patent number: 9087845
    Abstract: An electrically conductive device and a manufacturing method thereof are provided. According to an exemplary embodiment, an electrically conductive device includes a graphene layer on a substrate, a protein tube portion on the graphene layer, and a conductor penetrating through the protein tube portion to the graphene layer, wherein the conductor is in electrical contact with the graphene layer.
    Type: Grant
    Filed: December 4, 2014
    Date of Patent: July 21, 2015
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL CORPORATION (SHANGHAI), SEMICONDUCTOR MANUFACTURING INTERNATIONAL CORPORATION (BEIJING)
    Inventors: Xinpeng Wang, Haiyang Zhang
  • Publication number: 20150187908
    Abstract: Methods for fabricating semiconductor devices are provided. Gate structures are formed on a top surface of a substrate to form semiconductor devices. Trenches are formed in the substrate on both sides of each gate structure of each semiconductor device. The trenches on the both sides of each gate structure are filled with stress layers, the stress layers in the substrate protruding over the top surface of the substrate The stress layers are ion-doped and annealed on the both sides of each gate structure, and are pulse-etched to form a source region and a drain region of each gate structure. The pulse-etching is controlled such that the source regions and the drain regions of the plurality of semiconductor devices have a top surface coplanar with the top surface of the substrate.
    Type: Application
    Filed: October 21, 2014
    Publication date: July 2, 2015
    Inventors: HAIYANG ZHANG, JIA REN
  • Patent number: 9064819
    Abstract: This disclosure relates to a post-etch treating method. An opening is formed by etching a stacked structure of a dielectric layer, an intermediate layer and a metal hard mask layer arranged in order from bottom to top. The treating method sequentially comprises steps of: performing a first cleaning process on the stacked structure with the opening so as to remove at least a part of the metal hard mask layer; and performing a second cleaning process on the stacked structure with the opening so as to remove etching residues.
    Type: Grant
    Filed: December 7, 2011
    Date of Patent: June 23, 2015
    Assignee: Semiconductor Manufacturing Internation (Beijing) Corporation
    Inventors: Haiyang Zhang, Minda Hu, Junqing Zhou, Dongjiang Wang
  • Publication number: 20150137370
    Abstract: An electrically conductive device and a manufacturing method thereof are provided. According to an exemplary embodiment, an electrically conductive device includes a graphene layer on a substrate, a protein tube portion on the graphene layer, and a conductor penetrating through the protein tube potion to the graphene layer, wherein the conductor is in electrical contact with the graphene layer.
    Type: Application
    Filed: December 4, 2014
    Publication date: May 21, 2015
    Inventors: Xinpeng WANG, Haiyang ZHANG
  • Patent number: 9023224
    Abstract: The present disclosure pertains to a method of forming a spacer patterning mask. The method entails: providing a substrate; depositing, on the substrate, an interface layer, a core film and a first hard mask; patterning the core film and the first hard mask to form strips; depositing a spacer patterning layer to cover the core film and the first hard mask in the intermediate pattern; planarizing the spacer patterning layer by using the first hard mask in the intermediate pattern as a stop layer; etching the planarized spacer patterning layer; dry etching the second hard mask to expose the partially-etched spacer patterning layer; dry etching the exposed spacer patterning layer to form a spacer pattern; and removing the remaining first hard mask and second hard mask and the core film to obtain the final spacer patterning mask.
    Type: Grant
    Filed: May 15, 2014
    Date of Patent: May 5, 2015
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Xinpeng Wang, Haiyang Zhang
  • Patent number: 9003018
    Abstract: According to one embodiment of the present disclosure, a method for synchronizing data sets includes receiving a request to synchronize a first data set associated with a first server and a second data set associated with a second server. The method also includes determining, with reference to one or more replication constraints, whether to begin synchronization. The method further includes applying one or more resource control actions in response to determining to begin synchronization.
    Type: Grant
    Filed: September 15, 2011
    Date of Patent: April 7, 2015
    Assignee: CA, Inc.
    Inventors: Xiaopin (Hector) Wang, Shisheng (Victor) Liu, Guoxian Shang, Haiyang Zhang